NDLI: Synthesis of multiple-valued decision diagrams using current-mode CMOS circuits

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Synthesis of multiple-valued decision diagrams using current-mode CMOS circuits

Content Provider	IEEE Xplore Digital Library
Author	Abd-El-Barr, M. Fernandes, H.
Copyright Year	1999
Description	Author affiliation: Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia (Abd-El-Barr, M.)
Abstract	In this paper, an algorithm for generating modular designs of Ordered Multiple Decision Diagrams (OMDDs) for Current-Mode CMOS Logic (CMCL) implementation is introduced. The OMDD structures for a set of twelve benchmark circuits from the LGSynth93 using radices ranging from r=2 to r=10 are generated and compared in terms of size and speed. It is observed that MODDs with radices r/spl isin/(2, 4, 8) result in the smallest area. They also achieve the smallest normalized (with respect to the AT/sup 2/ measure for r=2) AT/sup 2/, where A is the area and T is the delay.
Starting Page	160
Ending Page	165
File Size	172909
Page Count	6
File Format	PDF
ISBN	0769501613
ISSN	0195623X
DOI	10.1109/ISMVL.1999.779711
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-05-20
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit synthesis CMOS logic circuits Delay estimation Semiconductor device measurement Data structures Boolean functions Decision trees Minimization Electronics packaging Neural networks
Content Type	Text
Resource Type	Article
Subject	Computer Science Mathematics

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