NDLI: Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)

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2015 IEEE International Symposium on Multiple-Valued Logic

2014 IEEE 44th International Symposium on Multiple-Valued Logic

2013 IEEE 43rd International Symposium on Multiple-Valued Logic

2012 IEEE 42nd International Symposium on Multiple-Valued Logic

2011 41st IEEE International Symposium on Multiple-Valued Logic

2010 40th IEEE International Symposium on Multiple-Valued Logic

2009 39th International Symposium on Multiple-Valued Logic

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Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)

Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)

Proceedings 1997 27th International Symposium on Multiple- Valued Logic

Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)

Proceedings 25th International Symposium on Multiple-Valued Logic

Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)

A four-valued logic and switch-level differences

A weak propositional calculus for signal processing with thresholds

On multiple-valued separable unordered codes

Multiple-valued combinational circuits with feedback

Multiple-valued-input TANT networks

Identification of linear ternary logic functions and its algorithms

Several remarks on algebraic entropy

Many-valued generalizations of two finite intervals in Post's lattice

Hereditary clones of multiple valued logic algebra

Design of fault-tolerant cellular arrays on multiple-valued logic

Complete test set for multiple-valued logic networks

Full sensitivity and test generation for multiple-valued logic circuits

Soft computing perspectives

An algebraic method to decide the deduction problem in many-valued propositional calculus

On T-quantifiers and S-quantifiers

Approximating propositional calculi by finite-valued logics

The satisfiability problem in multiple-valued Horn formulae

Efficient deduction in many-valued logics

Design of multiplex interconnection networks for massively parallel computing systems

Design of multiple-valued linear digital circuits for highly parallel k-ary operations

Design of multiwave computing circuits based on a model of integrated opto-electronic devices

Design of wave-parallel computing circuits for densely connected architectures

Interband-tunneling III-V semiconductor structures for multiple-valued literal and arithmetic functions

Resonant tunneling diodes for multi-valued digital applications

The completeness problem on the product of algebras of finite-valued logic

Completeness criteria in many-valued set logic under compositions with Boolean functions

Searching for complete functions over E(3) with small radii

Enumeration of function and bases of three-valued set logic under compositions with Boolean functions

Parallel processing of fuzzy inferences

Minimization for Kleene-Stone logic functions

On scheduling in multiprocessor systems using fuzzy logic

Spectral transformation of multiple-valued decision diagrams

CML current mode full adders for 2.5-V power supply

Multi-peak resonant tunneling diodes based fuzzifiers

A field programmable analog array for continuous, fuzzy, and multi-valued logic applications

Computing prime implicants/implicates for regular logics

Lattices of resolution logics

A design method for look-up table type FPGA by pseudo-Kronecker expansion

Calculation of Reed-Muller-Fourier coefficients of multiple-valued functions through multiple-place decision diagrams

Multiple-valued logic operations with universal literals

Efficient graph based representation of multi-valued functions with an application to genetic algorithms

Decomposition-based synthesis of multiple-valued functions for threshold logic network realization

A multiple-valued logic synthesis using the Kleenean coefficients

Algebraic division for multilevel logic synthesis of multi-valued logic circuits

Synthesis of multi-variable MVL functions using hybrid mode CMOS logic

Performance of CMOS current mode full adders

Multiple-valued current-mode MOS integrated circuits based on dual-rail source-coupled logic

Quaternary multiplier circuit

Digital circuit verification using partially-ordered state models

Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)

[1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic

[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic

[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic

Proceedings of the Twentieth International Symposium on Multiple-Valued Logic

Proceedings. The Nineteenth International Symposium on Multiple-Valued Logic

[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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