NDLI: First 32-bit SPARC-based processors implemented in high-speed CMOS

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First 32-bit SPARC-based processors implemented in high-speed CMOS

Content Provider	IEEE Xplore Digital Library
Author	Namjoo, M.
Copyright Year	1988
Description	Author affiliation: Sun Microsystem Inc., Mountain View, CA, USA (Namjoo, M.)
Abstract	The author presents an overview of the first two implementations of Sun Microsystems's scalable processor architecture (SPARC). The first implementation, MB86900, is designed using a 20000-gate 1.3- mu m CMOS gate-array. It operates at a clock rate of 16.6 MHz and delivers an average performance of 10 integer MIPS (millions of instruction per second). The second, CY7C601, is a full custom chip designed using a 0.8- mu m CMOS process. It operates at a clock rate of 33 MHz and delivers an average performance of 20 integer MIPS. The author discusses the basic features of these processors, their similarities and differences, and the tradeoffs used in their design. He also discusses the issues of design verification, test generation, and fault simulation.<>
Starting Page	374
Ending Page	376
File Size	285397
Page Count	3
File Format	PDF
ISBN	0818608722
DOI	10.1109/ICCD.1988.25726
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1988-10-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS process Registers Delay Sun Clocks Pipelines Coprocessors Testing Microprocessors Reduced instruction set computing
Content Type	Text
Resource Type	Article

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