NDLI: Approaching a nanosecond: a 32 bit adder

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Approaching a nanosecond: a 32 bit adder

Content Provider	IEEE Xplore Digital Library
Author	Bewick, G. Song, P. De Micheli, G. Flynn, M.J.
Copyright Year	1988
Description	Author affiliation: Comput. Syst. Lab., Stanford Univ., CA, USA (Bewick, G.; Song, P.; De Micheli, G.; Flynn, M.J.)
Abstract	The authors describe a high performance 32-bit binary adder designed at Stanford University. Measurements indicate that the adder computes the sum of two numbers (and a carry) in 2.1 ns and consumes 900 mW, using a power-supply voltage of -4.5 V. The adder is implemented using silicon emitter-coupled-logic circuitry with 0.5-V output swings. The high performance is a result of high-speed logic/technology and a special addition algorithm which results in an adder with a maximum of three levels of logic from any input to any output. The maximum fanout on any signal is eight input loads, the maximum number of inputs on any gate is five, and the maximum number of WIRE-OR outputs is eight.<>
Starting Page	221
Ending Page	226
File Size	364766
Page Count	6
File Format	PDF
ISBN	0818608722
DOI	10.1109/ICCD.1988.25695
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1988-10-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Adders Logic Computer networks Silicon Circuits Delay High performance computing Laboratories Power measurement Power supplies
Content Type	Text
Resource Type	Article

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