NDLI: Analysis and reduction of capacitive coupling noise in high-speed VLSI circuits

Content Provider	IEEE Xplore Digital Library
Author	Heydari, P. Pedram, M.
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA (Heydari, P.)
Abstract	Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2 GHz has caused crosstalk noise to become a serious problem, that degrades the performance and reliability of high speed integrated circuits. This paper presents an efficient method for computing the capacitive crosstalk in sub-quarter micron VLSI circuits. In particular, we provide closed-form expressions for the peak amplitude, the pulse width, and the time-domain waveform of the crosstalk noise. Experiments show that our analytical predictions are at least two times better than the previous models in terms of the prediction accuracy. More precisely, experimental results show that the maximum error of our predictions is less than 10% while the average error is only 4%. Finally, based on the proposed analytical models, we discuss the effects of transistor sizing and buffering on crosstalk noise reduction in VLSI circuits.
Sponsorship	IEEE Comput. Soc.
Starting Page	104
Ending Page	109
File Size	671766
Page Count	6
File Format	PDF
ISBN	0769512003
ISSN	10636404
DOI	10.1109/ICCD.2001.955011
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-09-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Noise reduction Crosstalk Very large scale integration Coupling circuits Integrated circuit noise Clocks Frequency Degradation Integrated circuit reliability High speed integrated circuits
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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