NDLI: Modeling crosstalk in resistive VLSI interconnections

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2015 28th International Conference on VLSI Design

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems

2012 25th International Conference on VLSI Design

2011 24th Internatioal Conference on VLSI Design

2010 23rd International Conference on VLSI Design

2009 22nd International Conference on VLSI Design

21st International Conference on VLSI Design (VLSID 2008)

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design

17th International Conference on VLSI Design. Proceedings.

16th International Conference on VLSI Design, 2003. Proceedings.

VLSI Design 2001. Fourteenth International Conference on VLSI Design

VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)

Bridging the gap between TCAD and ECAD methodologies in deep sub-micron interconnect extraction and analysis

Incorporating process induced effects into RC extraction

A new methodology for concurrent technology development and cell library optimization

A low-power digital camera-on-a-chip implemented in CMOS active pixel approach

A low-power wireless camera system

Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation

Low power code generation of multiplication-free linear transforms

Automatic insertion of gated clocks at register transfer level

Compact, ultra low power, programmable continuous-time filter banks for feedback cancellation in hearing aid

A low-complexity, reduced-power Viterbi Algorithm

A low power 256 KB SRAM design

Efficient techniques for reducing IDDQ observation time for sequential circuits

I/sub DDQ/-testability of tree circuits

Test-vector prediction of M-testable iterative arrays

A comparative study of pseudo stuck-at and leakage fault model

A new test compression scheme

IC layout and manufacturability: critical links and design flow implications

New and exact filling algorithms for layout density control

Design for manufacturing in the semiconductor industry: the Litho/Design Workshops

Interconnect simple, accurate and statistical models using on-chip measurements for calibration

MPEG-2 video data simulator: a case study in constrained HW-SW codesign

Processor modeling for hardware software codesign

Synthesis of DMA controllers from architecture independent descriptions of HW/SW communication protocols

Hierarchical conditional dependency graphs for mutual exclusiveness identification

Formal analysis of single WAIT VHDL processes for semantic based synthesis

Micro-2010: lead performance microprocessor of the year 2010-myth or reality?

Exact output response computation of RC interconnects under polynomial input waveforms

Sub-circuit analysis for power supply rejection ratio in regulated cascode operational transconductance amplifiers and filters

Efficient DC analysis of RVJ circuits for moment and derivative computations of interconnect networks

A three-tier assertion technique for SPICE verification of transistor level timing analysis

Timed circuit synthesis using implicit methods

A new approach for CMOS op-amp synthesis

Multi-valued logic synthesis

Sequential multi-valued network simplification using redundancy removal

Residue arithmetic multiplier based on the radix-4 signed-digit multiple-valued arithmetic circuits

Functional decomposition through structural analysis of decision diagrams-the binary and multiple-valued cases

Controlling state explosion in static simulation by selective composition

FzCRITIC-a functional timing verifier using a novel fuzzy delay model

Efficient simulation for hierarchical and partitioned circuits

Simulation and modeling of a multicast ATM switch

VERSE: a vector replacement procedure for improving test compaction in synchronous sequential circuits

Study of correlation of testability aspects of RTL description and resulting structural implementations

An approach to evaluating the effects of realistic faults in digital circuits

A low cost approach for detecting, locating, and avoiding interconnect faults in FPGA-based reconfigurable systems

Design and test of MEMS

Formal verification of an ARM processor

Formal verification of a snoop-based cache coherence protocol using symbolic model checking

An efficiently checkable subset of TCTL for formal verification of transition systems with delays

Superscalar processor validation at the microarchitecture level

Verifying Tomasulo's algorithm by refinement

Logic verification of very large circuits using Shark

Formal system design based on the synchrony hypothesis, functional models, and skeletons

Exploiting isomorphism for compaction and faster simulation of binary decision diagrams

Array index allocation under register constraints in DSP programs

Parallel implementation of 2D-discrete cosine transform using EPLDs

Improving area efficiency of residue number system based implementation of DSP algorithms

A design-in methodology to ensure first time success of complex digital signal processors

Synthesis of configurable architectures for DSP algorithms

Analytical expressions for power dissipation of macro-blocks in DSP architectures

Optimal retiming for initial state computation

Performance driven synthesis for pass-transistor logic

A state assignment scheme targeting performance and area

Efficient translation of statecharts to hardware circuits

Heuristic technology mapper for LUT based FPGAs

Efficient scheduling techniques for ROBDD construction

The retiming of single-phase clocked circuits containing level-sensitive latches

Recent advances in BDD based representations for Boolean functions: a survey

POWERTEST: a tool for energy conscious weighted random pattern testing

Simultaneous scheduling, binding and floorplanning for interconnect power optimization

Optimal voltages and sizing for low power [CMOS VLSI]

Digital circuit design for minimum transient energy and a linear programming method

Energy efficient datapath synthesis using dynamic frequency clocking and multiple voltages

GeneSys: a leaf-cell layout synthesis system for GHz VLSI designs

Near-optimum hierarchical layout synthesis of two-dimensional CMOS cells

COST: Circuit Optimization SysTem in ASIC library development environment

Interconnect optimization strategies for high-performance VLSI designs

Modeling crosstalk in resistive VLSI interconnections

Spec-based repeater insertion and wire sizing for on-chip interconnect

A test generator for segment delay faults

A complete characterization of path delay faults through stuck-at faults

A diagnostic fault simulator for fast diagnosis of bridge faults

Empirical computation of reject ratio in VLSI testing

Synthesis of symmetric functions for path-delay fault testability

Diagnostic test pattern generation for analog circuits using hierarchical models

Design considerations and implementations of a high performance dynamic register file

A VLSI architecture for on-line image decompression using GF(2/sup 8/) cellular automata

Lossy compression of images using logic minimization

Design, simulation and synthesis of an ASIC for fractal image coding

Quantum computation

FAAR: A router for field-programmable analog arrays

High performance MCM routing: a new approach

Sequential chaotic annealing and its application to multilayer channel routing

Satisfiability-based detailed FPGA routing

Improved effective capacitance computations for use in logic and layout optimization

A semi-digital delay locked loop for clock skew minimization

Component characterization and constraint transformation based on directed intervals for analog synthesis

Test generation for analog circuits using partial numerical simulation

Silicon-level physical verification of SubWavelength/sup TM/ designs

Design and implementation of a Viterbi decoder using FPGAs

TECHMIG: A layout tool for technology migration

Analysing forced oscillators with multiple time scales

Characterizing individual gate power sensitivity in low power design

Improving the diagnosability of digital circuits

Hierarchical delay fault simulation

Proceedings Eleventh International Conference on VLSI Design

Proceedings Tenth International Conference on VLSI Design

Proceedings of 9th International Conference on VLSI Design

Proceedings of the 8th International Conference on VLSI Design

Proceedings of 7th International Conference on VLSI Design

The Sixth International Conference on VLSI Design

The Fifth International Conference on VLSI Design

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