NDLI: Efficient symbolic support manipulation

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2015 33rd IEEE International Conference on Computer Design (ICCD)

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Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors

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Proceedings International Conference on Computer Design VLSI in Computers and Processors

Proceedings International Conference on Computer Design. VLSI in Computers and Processors

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Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors

Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93

A new modulo 2/sup a/+1 multiplier

Subterranean: A 600 Mbit/sec cryptographic VLSI chip

Concurrent error detection in nonlinear digital circuits with applications to adaptive filters

Fast CRC calculation

Quiescent current monitoring to improve the reliability of electronic systems in space radiation environments

Efficient diagnosis in algorithm-based fault tolerant multiprocessor systems

/spl Phi/-test: Perfect hashed index test for test response validation

Influence of error correlations on the signature analysis aliasing

An adaptive technique for dynamic rollback in concurrent event-driven fault simulation

Functional fault models and gate level coverage for sequential architectures

MIXER: Mixed-signal fault simulator

Pipelined fault simulation on parallel machines using the circuit flow graph

Newton: Performance improvement through comparative analysis

System-level specification of instruction sets

A framework for specifying and designing pipelines

Complex gate performance improvement by jog insertion into transistor gates

A logic-level model for /spl alpha/-particle hits in CMOS circuits

Computer-aided redesign of VLSI circuits for hot-carrier reliability

Test path generation and test scheduling for self-testable designs

Pseudoexhaustive BIST for sequential circuits

Design for testability of asynchronous sequential circuits

Efficient symbolic support manipulation

Some results on the complexity of Boolean functions for table look up architectures

High performance embedded system optimization using algebraic and generalized retiming techniques

A field programmable accelerator for compiled-code applications

Beyond superscalar using FPGAs

The Splash 2 processor and applications

Neighbour state transition method for VLSI optimization problems

An exact rectilinear Steiner tree algorithm

Strongly NP-hard discrete gate sizing problems

Partitioning and surmounting the software-hardware abstraction gap in an ASIC design project

System factorization in codesign. A case study of the use of formal techniques to achieve hardware-software decomposition

Fast timing analysis for hardware-software co-synthesis

Formal semantics of VHDL for verification of circuit designs

Physically realizable gate models

Derivation of a DRAM memory interface by sequential decomposition

Heuristic minimization of synchronous relations

Low-power driven technology mapping under timing constraints

Logic optimization with multi-output gates

Pica: An ultra-light processor for high-throughput applications

A systolic architecture for high speed pipelined memories

A systolic array for approximate string matching

String matching on IDP: a string matching algorithm for vector processors and its implementation

Design guidelines and testability assessment

Economics in design and test

Library-adaptively integrated data path synthesis for DSP systems

Cluster-oriented scheduling in pipelined data path synthesis

Global mobility based scheduling

Optimal scheduling of finite-state machines

Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation

ACES: a transient simulation strategy for integrated circuits

Analysis and control of timing jitter in digital logic arising from noise voltage sources

Multiple-page translation for TLB

Trail: a track-based logging disk architecture for zero-overhead writes

A memory controller with an integrated graphics processor

Analog automatic test plan generator-Integrating with modular analog IC design environment

A comparative evaluation of adders based on performance and testability

Reducing the cost of test pattern generation by information reusing

Hierarchical constraint solving in the parametric form with applications to efficient symbolic simulation based verification

Exploiting cofactoring for efficient FSM symbolic traversal based on the transition relation

An efficient symbolic design verification system

A novel clock distribution system for CMOS VLSI

A vector memory system based on wafer-scale integrated memory arrays

A three-dimensional mesh multiprocessor system using board-to-board free-space optical interconnects: COSINE-III

Hybrid number representations with bounded carry propagation chains

A note about the correction cycle of high radix Booth's multiplication

VLSI design of on-line add/multiply algorithms

Design of the Intel Pentium processor

Design methodology for GMICRO/500 TRON microprocessor

The PowerPC 601 design methodology

Synthesis of controllers from interval temporal logic specification

Specification and synthesis of a mixed-mode systems: Experiments in a VHDL environment

Efficient verification of symmetric concurrent systems

A reconfiguration-based yield enhancement system

Channel architecture optimization for performance and routability of row-based FPGAs

A new high performance field programmable gate array family

A C-testable carry-free divider

A 8.8-ns 54/spl times/54-bit multiplier using new redundant binary architecture

A 400 MHz wave-pipelined 8/spl times/8-bit multiplier in CMOS technology

Fault-tolerant content addressable memory

Hardware self-tuning and circuit performance monitoring

SMAC: A scene matching chip

A comparison of synchronous and asynchronous FSMD designs

An efficient unique state coding algorithm for signal transition graphs

An algorithm for exact bounds on the time separation of events in concurrent systems

ASLCScan: A scan design technique for asynchronous sequential logic circuits

Bit-splitting for testability enhancement in scan-based design

Synthesis of sequential circuits for easy testability through performance-oriented parallel partial scan

A partial scan cost estimation method at the system level

The spring scheduling co-processor: a scheduling accelerator

Evaluation of an object-caching coprocessor design for object-oriented systems

Speculative computation for coprocessor synthesis

An integrated environment for concurrent development of a pixel processor ASIC and application software

Speculative execution and reducing branch penalty in a parallel issue machine

Area and performance comparison of pipelined RISC processors implementing different precise interrupt methods

Determining cost-effective multiple issue processor designs

Architecture-compatible code boosting for performance enhancement of the IBM RS/6000

Fidelity and near-optimality of Elmore-based routing constructions

Statistical timing optimization of combinational logic circuits

A path sensitization approach to area reduction

An analysis of path sensitization criteria

AMBIANT: automatic generation of behavioral modifications for testability

Towards a methodology for the formal hierarchical verification of RISC processors

Hardware verification using symbolic state transition graphs

An intelligent I-cache prefetch mechanism

About set and skewed associativity on second-level caches

A split data cache for superscalar processors

The structure of assignment, precedence, and resource constraints in the ILP approach to the scheduling problem

Lower bounds on the iteration time and the number of resources for functional pipelined data flow graphs

A recursive technique for computing lower-bound performance of schedules

Wearable computers: Merging information space with the workspace

Symbolic analysis methods for masks, circuits and systems

Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93

Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors

Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors

Proceedings 1988 IEEE International Conference on Computer Design: VLSI

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