NDLI: A pulse-to-static conversion latch with a self-timed control circuit

Content Provider	IEEE Xplore Digital Library
Author	Wei Hwang Joshi, R.V. Henkels, W.H.
Copyright Year	1997
Description	Author affiliation: IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA (Wei Hwang)
Abstract	The design and experimental demonstration of a low-power pulse-to-static conversion latch circuit is described. The circuit includes self-timed control and a 64-bit latch array, both designed utilizing self-resetting CMOS (SRCMOS) circuit techniques. The self-timed feature of the control requires only one system clock input. The evaluation, reset and write-enable controls are all generated within a control macro. The latch is level sensitive scan design (LSSD) compatible and complies with SRCMOS test modes. Use of these latches facilitates the synchronization, pipelined operation, power-management, and testing of advanced digital systems employing a mix of static and dynamic circuits to achieve high performance. An experimental 64-bit latch array and self-timed control macro, designed for 2.5 V-0.5 /spl mu/m CMOS technology, has been successfully fabricated and tested. The full circuit occupies an area of 1.704 mm/spl times/0.07 mm, and the size of latch bit cell is 21.6 /spl mu/m/spl times/70 /spl mu/m. Experimental results have shown the conversion latch to function properly, capturing 1.2 ns output pulses from an SRCMOS register file, and properly converting them to static levels. The measured delay from global clock to static output was 725 ps.
Starting Page	712
Ending Page	717
File Size	643398
Page Count	6
File Format	PDF
ISBN	081868206X
ISSN	10636404
DOI	10.1109/ICCD.1997.628943
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Latches Circuit testing CMOS technology Clocks Pulse circuits Control systems Synchronization System testing Digital systems Automatic testing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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