NDLI: On the diminished-1 modulo $2^{N}+1$ fused multiply-add units

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On the diminished-1 modulo $2^{N}+1$ fused multiply-add units

Content Provider	IEEE Xplore Digital Library
Author	Efstathiou, C. Voyiatzis, I.
Copyright Year	2011
Description	Author affiliation: Dept. of Informatics, TEI of Athens, Ag. Spyridonos Str., 12210 Egaleo, Athens, Greece (Efstathiou, C.; Voyiatzis, I.)
Abstract	In this work the most efficient modulo $2^{n}+1$ multiplication algorithm for diminished-1 operands proposed to date is extended to compute expressions of the form \|A×B + D\|2n+1. The derived partial products are reduced by a carry save adder tree to two operands, which are finally added by a modulo $2^{n}+1$ adder. The proposed architecture can find applicability in systems in which fused multiply-add units can accelerate the execution of the targeting algorithms, for example digital signal processing and cryptography systems.
Starting Page	1
Ending Page	5
File Size	309502
Page Count	5
File Format	PDF
ISBN	9781612848990
e-ISBN	9781612849003
DOI	10.1109/DTIS.2011.5941427
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-06
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis DSP modulo $2^{n}+1$ diminished-1 Delay multiply-add unit Signal processing algorithms RNS Computer architecture Digital signal processing Logic gates Residue number system Adders
Content Type	Text
Resource Type	Article

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