NDLI: Vade mecum on side-channels attacks and countermeasures for the designer and the evaluator

Content Provider	IEEE Xplore Digital Library
Author	Guilley, S. Meynard, O. Nassar, M. Duc, G. Hoogvorst, P. Maghrebi, H. Elaabid, A. Bhasin, S. Souissi, Y. Debande, N. Sauvage, L. Danger, J.
Copyright Year	2011
Description	Author affiliation: Institut TELECOM / TELECOM ParisTech, CNRS LTCI (UMR 5141), Département COMELEC, 46 rue Barrault, 75634 PARIS Cedex 13, France (Guilley, S.; Meynard, O.; Nassar, M.; Duc, G.; Hoogvorst, P.; Maghrebi, H.; Elaabid, A.; Bhasin, S.; Souissi, Y.; Debande, N.; Sauvage, L.; Danger, J.)
Abstract	Implementation-level attacks are nowadays well known and most designers of security embedded systems are aware of them. However, both the number of vulnerabilities and of protections have seriously grown since the first public reporting of these threats in 1996. It is thus difficult to assess the correct countermeasures association to cover all the possible attack paths. The goal of this paper is to give a clear picture of the possible adequation between actually risks and mitigation techniques. A specific focus is made on two protection techniques addressing primarily side-channel attacks: masking and hiding. For the first time, we provide with a way to estimate a tradeoff depending on the environmental conditions (amount of noise) and on the designer skills (ability to balance the design). This tradeoff is illustrated in a decision diagram, helpful for the security designer to justify choices and to account for the cost overhead.
Starting Page	1
Ending Page	6
File Size	273736
Page Count	6
File Format	PDF
ISBN	9781612848990
e-ISBN	9781612849003
DOI	10.1109/DTIS.2011.5941419
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-06
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	hiding and masking Correlation Noise Implementation-level attacks comparison of countermeasures Analytical models decision diagram for the designer side-channel attacks Software Timing Cryptography Mathematical model leakage metric
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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