NDLI: GPU-based timing-aware test generation for small delay defects

Content Provider	IEEE Xplore Digital Library
Author	Kuan-Yu Liao Po-Juei Chen Ang-Feng Lin Li, J.C.-M. Hsiao, M.S. Laung-Terng Wang
Copyright Year	2014
Description	Author affiliation: Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Kuan-Yu Liao; Po-Juei Chen; Ang-Feng Lin; Li, J.C.-M.) \|\| Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA (Hsiao, M.S.) \|\| SynTest Technol., Inc., Sunnyvale, CA, USA (Laung-Terng Wang)
Abstract	A GPU-based timing-aware ATPG is proposed to generate a compact high-quality test set. The test generation algorithm backtraces and propagates along multiple long paths so that many test patterns are generated at the same time. Generated test patterns are then fault simulated and selected. Compared with an 8-core CPU-based timing-aware commercial ATPG, the proposed GPU-based technique achieved 36% test length reductions on large benchmark circuits while the SDQL quality remains almost the same.
Sponsorship	IEEE Counc. Electron. Design Autom.
Starting Page	1
Ending Page	2
File Size	410650
Page Count	2
File Format	PDF
ISBN	9781479934157
DOI	10.1109/ETS.2014.6847835
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-26
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic test pattern generation Circuit faults Delays Load modeling Kernel Graphics processing units Integrated circuit modeling parallel GPU test generation small delay defect
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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