NDLI: Hybrid BIST using partially rotational scan

Content Provider	IEEE Xplore Digital Library
Author	Ichino, K. Asakawa, T. Fukumoto, S. Iwasaki, K. Kajihara, S.
Copyright Year	2001
Description	Author affiliation: Tokyo Metropolitan Univ., Japan (Ichino, K.)
Abstract	Developed a partially rotational scan (PRS) register used for the n-detection BIST (built-in self-test) that can detect not only delay faults but also unmodeled faults. The developed circuit consists of a shift register with partial rotation. Also presents a procedure for selecting test vectors from ATPG (automatic test pattern generation) ones. This testing method enables at-speed testing and the stuck-at fault coverage of n/spl times/100% by using subset of the ATPG vectors. And it drastically reduces the number of vectors input from an external low-speed tester. Computer simulations of stuck-at fault coverage are conducted on ISCAS'85, ISCAS'89, and ITC'99 circuits for detection times n of 1, 2, 3, 5, 10, and 15. They show that the compaction rates of the ATPG test vectors range from 52.4% (s713) to 0.9% (c499) of origin. This result demonstrates that the PRS register can accomplish low-cost, at-speed testing.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	379
Ending Page	384
File Size	498131
Page Count	6
File Format	PDF
ISBN	0769513786
ISSN	10817735
DOI	10.1109/ATS.2001.990313
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-11-19
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Circuit testing Circuit faults Automatic test pattern generation Electrical fault detection Fault detection Delay Shift registers Automatic testing Computer simulation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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