NDLI: Exploiting BIST approach for two-pattern testing

Content Provider	IEEE Xplore Digital Library
Author	Xiaowei Li Cheung, P.Y.S.
Copyright Year	1998
Description	Author affiliation: Dept. of Electr. & Electron. Eng., Hong Kong Univ., Hong Kong (Xiaowei Li)
Abstract	Detection of delay and transistor stuck-open faults requires two-pattern tests. BIST provides a low-cost test solution. This paper exploits the BIST approach for two-pattern testing. The generation of a pseudo-deterministic test-pair sequence with LFSR was exploited. A three-step approach is proposed. First, a set of deterministic test-pair is generated to detect all robust path delay faults. Second, LFSR-based TPG configurations are calculated to have pre-generated test-pair embedded in a set of maximal length pseudo-random test sequences. Third, a global cost-optimal BIST solution for data path (using pseudo-deterministic TPGs) is proposed. The second step is formulated as a cluster-covering problem. The third step is formulated as an 0-1 ILP. Experimental results are presented to demonstrate the effectiveness of the proposed approach.
Starting Page	424
Ending Page	429
File Size	653956
Page Count	6
File Format	PDF
ISBN	0818682779
ISSN	10817735
DOI	10.1109/ATS.1998.741651
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-12-02
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Circuit testing Circuit faults Fault detection Test pattern generators Delay AC generators Automatic testing Electrical fault detection Electronic equipment testing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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