NDLI: Design of a comparator in CMOS SOI

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2006 6th International Workshop on System on Chip for Real Time Applications

Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)

4th IEEE International Workshop on System-on-Chip for Real-Time Applications

4th IEEE International Workshop on System-on-Chip for Real-Time Applications

Proceedings 4th IEEE International Workshop on System-on-Chip for Real-Time Applications

Proceedings 4th IEEE International Workshop on System-on-Chip for Real-Time Applications

Table of contents

Message from the Chairs

Program Committee

SoC integration challenges

Automated fixing of complex/process critical DRC violations in place and route systems using calibre in the synopsys/milkyway environment

Integrating a single physical verification tool for systems-on-chip designs

High-speed I/Os and PLLs for data communication applications

Formal verification of digital circuits

Silicon modeling of nanometer systems-on-chip

Beyond P-cell and gate-level: accuracy requirements for simulation of nanometer SoC design

A real-time architecture of SOC selective gas sensor array using KNN based on the dynamic slope and the steady state response

A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter

Interface-based design of systems-on-chip using UML-RT

Using design patterns for type unification and introspection in SystemC

A framework for implementing reusable digital signal processing modules

An optimal charge balancing model for fast distributed SystemC simulation in IP/SoC design

A programmable base MDLNS MAC with self-generated lookup table

64-bit hybrid dual-threshold voltage power-aware conditional carry adder design

FPGA implementation of fast radix 4 division algorithm

CRT-based three-prime RSA with immunity against hardware fault attack

RNS application for digital image processing

Using integer equations to check PSL properties in RT level design

Verification strategy determination using dependence analysis of transaction-level models

Consistency validation of high-level requirements

An accurate low iteration algorithm for effective capacitance computation

An embedded tester core for system-on-chip architectures

An intellectual property module for auto-calibration of time-interleaved pipelined analog-to-digital converters

10 GHz PLL using active shunt-peaked MCML gates and improved frequency acquisition XOR phase detector in 0.18 /spl mu/m CMOS

A CMOS high-voltage DC-DC up converter dedicated for ultrasonic applications

Possible noise failure modes in static and dynamic circuits

Simulation-in-the-loop analog circuit sizing method using adaptive model-based simulated annealing

A scalable low-voltage extended swing CMOS LC quadrature VCO for RF transceivers

Ultra low noise signed digit arithmetic using cellular neural networks

Integrated hardware-software platform for image processing applications

An efficient VLSI implementation of MC interpolation for MPEG-4

A novel memory architecture for real-time mesh-based video motion compensation

A 2-D forward/inverse integer transform processor of H.264 based on highly-parallel architecture

Real-time audio/video decoders for digital multimedia broadcasting

Empirical analysis of operand usage and transport in multimedia applications

MPEG-4 FGS encoder design for an interactive content-aware MPEG-4 video streaming SOC

Observability-based RTL simulation using Java

A step towards intelligent translation from high-level design to RTL

Towards automating hardware/software co-design

Development of timing driven IP design flow based on physical knowledge synthesis

Taking mixed-signal substrate noise coupling simulation to the behavioral level using SystemC

Data-flow timing models of dynamic multimedia applications for multiprocessor systems

Design strategies for ESD protection in SOC

Bit memory instructions for a general CPU

Accurate on-chip variation modeling to achieve design for manufacturability

A parameterized cell-based design approach for digital-to-analog converters

Design of a comparator in CMOS SOI

A sigma-delta modulator for digital hearing instruments using 0.18/spl mu/m CMOS technology

A fully automated approach for analog circuit reuse

Interfacing in microprocessor-based systems with an advanced physical addressing

SERDES technology for gigabit I/O communications in storage area networking

Evaluation of MP-SoC interconnect architectures: a case study

A power-efficient, low-complexity, memoryless coding scheme for buses with dominating inter-wire capacitances

Interconnect synthesis for systems on chip

Network on chip simulations for benchmarking

Non-redundant coding for deep sub-micron address buses

RtrASSoc - adaptable superscalar reconfigurable programmable system on chip - the embedded operating system - EOS

A model for a reusable system-on-a-chip hardware component integrated with design exploration methodology

ECOMIPS: an economic MIPS CPU design on FPGA

A field programmable bit-serial digital signal processor

A customizable embedded SoC platform architecture

SOC design of an IF subsampling terminal for a gigabit wireless LAN with asymmetric equalization

Reconfigurable 2.5 GHz phase-locked loop for system on chip applications

SoC features for a multi-processor WCDMA base-station modem

The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.

Design of a comparator in CMOS SOI

Content Provider	IEEE Xplore Digital Library
Author	Sall, E. Vesterbacka, M.
Copyright Year	2004
Description	Author affiliation: Dept. of E.E., Linkoping Univ., Sweden (Sall, E.; Vesterbacka, M.)
Abstract	This paper gives an introduction to the silicon-on-insulator (SOI) CMOS technology and presents the major advantages and disadvantages of using SOI. It also presents the design of a comparator, which has been sent for manufacturing, designed in a 0.13 /spl mu/m partially depleted SOI CMOS process. The comparator is a first step towards the design of a complete 6-bit flash analog-to-digital converter, with a sampling frequency of 1.5 GHz.
Sponsorship	IEEE Circuits and Syst. Soc. Micronet R&D iCore Univ. of Calgary, Canada Alberta Innovations and Sci
Starting Page	229
Ending Page	232
File Size	415828
Page Count	4
File Format	PDF
ISBN	0769521827
DOI	10.1109/IWSOC.2004.1319884
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-07-19
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon on insulator technology MOSFET circuits Body regions Threshold voltage Impact ionization Thin film devices CMOS technology CMOS process Analog-digital conversion Sampling methods
Content Type	Text
Resource Type	Article

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