NDLI: Energy efficient bootstrapped CMOS large RC-load driver circuit for ultra low-voltage VLSI

Content Provider	IEEE Xplore Digital Library
Author	Chien-Yu Lu Ching-Te Chuang
Copyright Year	2010
Description	Author affiliation: Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R. O. C. (Chien-Yu Lu; Ching-Te Chuang)
Abstract	This paper presents an energy efficient bootstrapped CMOS driver to enhance switching speed for driving large RC load for ultra low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve more positive and negative boosted voltage levels and to allow the boosted nodes to maintain the boosted levels, thus improving boosting efficiency and enhancing the switching speed. Performance evaluation based on UMC 65nm low power technology (Vtn≈Vtp≈0.5v) indicates that the proposed driver provides rising-delay improvement of 24%–56% and falling-delay improvement of 9%–30% at V = 0.3 V for 1 to 10 segments of large distributed RC loading, as compared with the conventional bootstrapped driver consuming the same power. Although designed and optimized for ultra low-voltage operation, the proposed bootstrapped driver is shown to be advantageous at high supply voltage as well.
Starting Page	70
Ending Page	73
File Size	556408
Page Count	4
File Format	PDF
ISBN	9781424452699
DOI	10.1109/VDAT.2010.5496694
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-26
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy efficiency Driver circuits Very large scale integration Boosting Threshold voltage Switching circuits Energy consumption Power engineering and energy Design optimization CMOS technology
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSI

A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI

Enhanced bootstrapped CMOS driver for large RC-load and ultra-low voltage VLSI

A direct bootstrapped CMOS large capacitive-load driver circuit

Efficiency of adiabatic logic for low-power, low-noise VLSI

A bootstrapped CMOS circuit technique for low-voltage application

UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI

Low-voltage SOI CMOS DTMOS/MTCMOS circuit technique for design optimization of low-power SOC applications

Low power synthesis of dual threshold voltage CMOS VLSI circuits

Energy efficient bootstrapped CMOS large RC-load driver circuit for ultra low-voltage VLSI

Similar Documents

Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSI

A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI

Enhanced bootstrapped CMOS driver for large RC-load and ultra-low voltage VLSI

A direct bootstrapped CMOS large capacitive-load driver circuit

Efficiency of adiabatic logic for low-power, low-noise VLSI

A bootstrapped CMOS circuit technique for low-voltage application

UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI

Low-voltage SOI CMOS DTMOS/MTCMOS circuit technique for design optimization of low-power SOC applications

Low power synthesis of dual threshold voltage CMOS VLSI circuits

Energy efficient bootstrapped CMOS large RC-load driver circuit for ultra low-voltage VLSI