NDLI: 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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VLSI Design, Automation and Test(VLSI-DAT)

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2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

Native-Mode Self Test for Embedded Systems on a Chip

Nanoelectronics: challenges and opportunities

Challenges of Digital Consumer and Mobile SoC's: More Moore Possible?

Microprocessor Modeling and Simulation with SystemC

A Memory-Efficient Progressive JPEG Decoder

An LLC-OCV Methodology for Statistic Timing Analysis

A Matching-based Placement and Routing System for Analog Design

Test Power IR Drop Closure Flow for NetComposer-I Platform Design

4-Mb SPI Flash Compatible Phase-Change Memory

A Low-Power Low-Swing Single-Ended Multi-Port SRAM

A 256×128 Energy-Efficient TCAM with Novel Low Power Schemes

Design on Mixed-Voltage I/O Buffers with Consideration of Hot-Carrier Reliability

Minimizing Energy Consumption with Variable Forward Body Bias for Ultra-Low Energy LSIs

Maximizing Full-Chip Simulation Signal Visibility for Efficient Debug

Reducing Transaction-Level Modeling Effort while Retaining Low Communication Overhead for HW/SW Co-Emulation System

Designing Globally Optimal Delta-Sigma Modulator Topologies via Signomial Programming

On-Chip Bus Encoding for Power Minimization Under Delay Constraint

A 4-Channel Poly-Phase Filter for Cognitive Radio Systems

Analysis and Design of a 1V Charge Sampling Readout Amplifier in 90nm CMOS for Medical Imaging

A 6Gbps Serial Link Transmitter with Pre-emphasis

Challenges for Low-power Embedded SOC's

Mixed Hardware Software Multilevel Modeling and Simulation for Multithreaded Heterogeneous MPSoC

Low-Power Instruction Cache Architecture Using Pre-Tag Checking

Low Cost Testing of Quadruple Band GSM RFCMOS SOC

Testing Crosstalk Faults of Data and Address Buses in Embedded RAMs

A Power-Saved 1Gbps Irregular LDPC Decoder based on Simplified Min-Sum Algorithm

A Low-Power Viterbi Decoder Based on Scarce State Transition and Variable Truncation Length

Generalized MLP/BP-based MIMO DFEs for Overcoming ISI and ACI in Band-limited Channels

A Dynamic Phase-Frequency Recovery for Power Reduction in OFDM Systems

Challenges and Solutions in Modern VLSI Placement

Microarchitecture-Aware Floorplanning for Processor Performance Optimization

Interleaving of Gate Sizing and Constructive Placement for Predictable Performance

λ-geometry clock tree construction with wirelength and via minimization

A Low-Complexity Fractional Delay All-Pass Filter Design for Time-Domain Interpolation

JQRPSD Detection with Low Complexity for SDM MIMO Wireless Communication System

Synchronous Sampling and SNR-Based Gain Control in DS/CDMA Systems

A 1V 5-Bit 5GSample/sec CMOS ADC for UWB Receivers

A 4-Bit, 13.5GSample/sec Track-and-Hold Circuit

A 1V 10-Bit 400MS/s Current-Steering D/A Converter in 90-nm CMOS

Post-Silicon Design Methodology on Chip Power Characterization, Validation, and Debug Applied on High Performance Per Watt Microprocessor

Toward Automatic Synthesis of SOC Test Platforms

Stable Performance MAC Protocol for HOY Wireless Tester under Large Population

A 30Phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery

A Self-Calibrated Multiphase DLL-Based Clock Generator

Novel Configurable Architecture of ML-Decomposed Binary Arithmetic Encoder for Multimedia Applications

A Hardwired Context-Based Adaptive Binary Arithmetic Encoder for H. 264 Advanced Video Coding

A Joint Architecture of Error-Concealed Deblocking Filter for H.264/AVC Video Transmission

A 2.4-GHz 18-mW Two-Point Delta-Sigma Modulation Transmitter for IEEE 802.15.4

A Digital Envelope Modulator for an OFDM WLAN Polar Transmitter in 90 nm CMOS

On-Chip Transmission Line Modeling and Applications to Millimeter-Wave Circuit Design in 0.13um CMOS Technology

Two-Stage Scattered Pilot Synchronization with Channel Estimation Scattered Pilots Pre-Filling for DVB-T/H

Low Power and Power Aware Design for DVB-T/H Baseband Inner Receiver

Multilevel LINC System Design for Wireless Transmitters

A 4-54GHz Static Frequency Divider with Back-Gate Coupling

A LC-Tank Injection Locked Frequency Divider with Complementary Structure

Low Phase Noise Differential CMOS VCO Based on Tapped-Inductor Resonator

Efficient Memory-Based FFT Architectures for Digital Video Broadcasting (DVB-T/H)

Power Gating Technique for Embedded Pseudo SRAM

Efficient Calculation of Timed Cumulative Probability Density Function

Input Selection Encoding for Low Power Multiplexer Tree

Automation of Synchronous Bias Transmission Line Pulsing System

An Efficient Design-for-Testability Scheme for Motion Estimation in H.264/AVC

Characterization of Supply and Substrate Noises in CMOS Digital Circuits

Hardware Architecture Design of CABAC Codec for H.264/AVC

Design and Implementation of Reconfigurable RSA Cryptosystem

On-Chip VDC Circuit for SRAM Power Management

Switch Controlled Source Amplifier for Low Power Mobile TFT-LCD Driver IC

The novel Chinese abacus adder

Theoretical Analysis and Implementation of a Variable Gain Even Harmonic Mixer

Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector

A Realization of Low Noise Silicon Acoustic Transducer Interface Circuit

2006 International Symposium on VLSI Design, Automation and Test

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).

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