NDLI: Application specific multi-port memory customization in FPGAs

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2015 25th International Conference on Field Programmable Logic and Applications (FPL)

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

Table of content

Biomedical image processing and reconstruction with dataflow computing on FPGAs

FPGA implementation of low-power split-radix FFT processors

Efficient multi-standard cognitive radios on FPGAs

Using high-level knowledge to enhance data channels in FPGA streaming systems

A combination of multi-edge coding and independent coding lines for time-to-digital conversion

Hardware conversion of neural networks simulation models for neural processing accelerator implemented as FPGA-based SoC

Enabling SRAM-PUFs on Xilinx FPGAs

A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAs

A fast and scalable FPGA damage diagnostic service for R3TOS using BIST cloning technique

Ultrasmall: The smallest MIPS soft processor

A soft-core processor for finite field arithmetic with a variable word size accelerator

Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy

Aging effects in FPGAs: an experimental analysis

Efficient implementation of a single-precision floating-point arithmetic unit on FPGA

Run-time accelerator binding for tile-based mixed-grained reconfigurable architectures

Scalable parallel architecture for singular value decomposition of large matrices

A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems

Achieving portability and efficiency over chip heterogeneous multiprocessor systems

Multi-FPGA reconfigurable system for accelerating MATLAB simulations

MAPC: Memory access pattern based controller

Asynchronously assisted FPGA for variability

Experimental multi-FPGA GNSS receiver platform

RAM-based hardware accelerator for network data anonymization

Heterogeneous dataflow architectures for FPGA-based sparse LU factorization

An FPGA sliding window-based architecture harris corner detector

Accelerate NDN name lookup using FPGA: Challenges and a scalable approach

FPGA acceleration of short read mapping based on sort and parallel comparison

FPGA acceleration of SAT/Max-SAT solving using variable-way cache

An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applications

Low-cost multiplier-based FPU for embedded processing on FPGA

THOR - The hardware onion router

Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm

High throughput channel tracking for JTRS wireless channel emulation

Particle filtering-based Maximum Likelihood Estimation for financial parameter estimation

A high performance alternating projections image demosaicing hardware

A scalable, high-performance customized priority queue

Privacy preserving large scale DNA read-mapping in MapReduce framework using FPGAs

Accurate power control and monitoring in ZYNQ boards

Fast and accurate SEU-tolerance characterization method for Zynq SoCs

Area implications of memory partitioning for high-level synthesis on FPGAs

Incremental distributed trigger insertion for efficient FPGA debug

Efficient mapping of mathematical expressions into DSP blocks

Leakage and performance aware resource management for 2D dynamically reconfigurable FPGA architectures

Mixed-architecture process scheduling on tightly coupled reconfigurable computers

Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security

Towards domain-specific Instruction-Set Generation

An image processing library for C-based high-level synthesis

Rapid codesign of a soft vector processor and its compiler

Application specific multi-port memory customization in FPGAs

An enhanced and embedded GNU radio flow

A secure and unclonable embedded system using instruction-level PUF authentication

Pattern-based FPGA logic block and clustering algorithm

An FPGA hardware acceleration of the indirect calculation of tree lengths method for phylogenetic tree reconstruction

A mixed integer linear programming approach for design space exploration in FPGA-based MPSoC

Automatic high-level synthesis of multi-threaded hardware accelerators

High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs

Methods for implementation of feedback loops in high speed FPGA applications

A design support tool set for asynchronous circuits with bundled-data implementation on FPGAs

flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms

A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms

A high speed design and implementation of dynamically reconfigurable processor using 28NM SOI technology

Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor

Using an OpenCL framework to evaluate interconnect implementations on FPGAs

HPC-gSpan: An FPGA-based parallel system for frequent subgraph mining

High level programming framework for FPGAs in the data center

Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring

Ready PCIe data streaming solutions for FPGAs

Educating hardware design — From primary school children to postgraduate engineers

FPGA implementation of a multi-algorithm parallel FEC for SDR platforms

Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration

Multi-directional error correction schemes for SRAM-based FPGAs

Robust and flexible FPGA-based digital PUF

High-throughput implementation of a million-point sparse Fourier Transform

Power-efficient re-gridding architecture for accelerating Non-uniform Fast Fourier Transform

Radix-4 and radix-8 booth encoded interleaved modular multipliers over general F

Dataflow acceleration of Krylov subspace sparse banded problems

Hardware system synthesis from Domain-Specific Languages

Evolutionary on-line synthesis of hardware accelerators for software modules in reconfigurable embedded systems

Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays

Method for dynamic power monitoring on FPGAs

HyPER: A runtime reconfigurable architecture for monte carlo option pricing in the Heston model

An efficient and flexible host-FPGA PCIe communication library

A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory

A semi-supervised modeling approach for performance characterization of FPGA architectures

A highly-efficient and green data flow engine for solving euler atmospheric equations

An efficient FPGA-based hardware framework for natural feature extraction and related Computer Vision tasks

An efficient sparse conjugate gradient solver using a Beneš permutation network

Efficient 3D triangulation in hardware for dense structure-from-motion in low-speed automotive scenarios

Pipelined reconfigurable multiplication with constants on FPGAs

Comparing soft and hard vector processing in FPGA-based embedded systems

Pipelined compressor tree optimization using integer linear programming

Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory use

Exploring architecture parameters for dual-output LUT based FPGAs

Adaptive Dynamic On-chip Memory Management for FPGA-based reconfigurable architectures

Interconnect for commodity FPGA clusters: Standardized or customized?

FPGA implementation of an interior point method for high-speed model predictive control

Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing

High-precision self-characterization for the LUT burn-in information leakage threat

Criticality-aware scrubbing mechanism for SRAM-based FPGAs

Secure partial dynamic reconfiguration with unsecured external memory

Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs

Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data

Portable module relocation and bitstream compression for Xilinx FPGAs

A scalable, serially-equivalent, high-quality parallel placement methodology suitable for modern multicore and GPU architectures

A survey of open source processors for FPGAs

Trends of CPU, GPU and FPGA for high-performance computing

An empirical evaluation of High-Level Synthesis languages and tools for database acceleration

TransPar: Transformation based dynamic Parallelism for low power CGRAs

Body bias control for a coarse grained reconfigurable accelerator implemented with Silicon on Thin BOX technology

Caching memcached at reconfigurable network interface

The LEAP FPGA operating system

Heterogeneous Heartbeats: A framework for dynamic management of Autonomous SoCs

Modulo SDC scheduling with recurrence minimization in high-level synthesis

Hierarchical reconfiguration of FPGAs

PR-HMPSoC: A versatile partially reconfigurable heterogeneous Multiprocessor System-on-Chip for dynamic FPGA-based embedded systems

A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs

FPGA architecture support for heterogeneous, relocatable partial bitstreams

New approaches for in-system debug of behaviorally-synthesized FPGA circuits

Source-level debugging for FPGA high-level synthesis

Transparent insertion of latency-oblivious logic onto FPGAs

Effective FPGA debug for high-level synthesis generated circuits

Hardware accelerated novel optical de novo assembly for large-scale genomes

Compiling text analytics queries to FPGAs

Automated framework for FPGA-based parallel genetic algorithms

Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration

Run-time power gating in hybrid ARM-FPGA devices

Towards dark silicon era in FPGAs using complementary hard logic design

Improving FPGA accelerated tracking with multiple online trained classifiers

Patra: Parallel tree-reweighted message passing architecture

DyRACT: A partial reconfiguration enabled accelerator and test platform

2013 23rd International Conference on Field programmable Logic and Applications

22nd International Conference on Field Programmable Logic and Applications (FPL)

2011 21st International Conference on Field Programmable Logic and Applications

2010 International Conference on Field Programmable Logic and Applications

2009 International Conference on Field Programmable Logic and Applications

2008 International Conference on Field Programmable Logic and Applications

2007 International Conference on Field Programmable Logic and Applications

2006 International Conference on Field Programmable Logic and Applications

International Conference on Field Programmable Logic and Applications, 2005.

Application specific multi-port memory customization in FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Malazgirt, G.A. Yantir, H.E. Yurdakul, A. Niar, S.
Copyright Year	2014
Description	Author affiliation: LAMIH, Univ. of Valenciennes, Valenciennes, France (Niar, S.) \|\| Comput. Eng., Bogazici Univ., Istanbul, Turkey (Malazgirt, G.A.; Yantir, H.E.; Yurdakul, A.)
Abstract	FPGA block RAMs (BRAMs) offer speed advantages compared to LUT-based memory designs but a BRAM has only one read and one write port. Designers need to use multiple BRAMs in order to create multi-port memory structures which are more difficult than designing with LUT-based multiport memories. Multi-port memory designs increase overall performance but comes with area cost. In this paper, we present a fully automated methodology that tailors our multi-port memory from a given application. We present our performance improvements and area tradeoffs on state-of-the-art string matching algorithms.
Starting Page	1
Ending Page	4
File Size	262059
Page Count	4
File Format	PDF
ISBN	9783000446450
DOI	10.1109/FPL.2014.6927426
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-02
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Technical University of Munich (TUM)
Subject Keyword	Parallel processing Field programmable gate arrays Random access memory Program processors Pattern matching Registers Ports (Computers)
Content Type	Text
Resource Type	Article

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