NDLI: Datapath scheduling using dynamic frequency clocking

Content Provider	IEEE Xplore Digital Library
Author	Mohanty, S.P. Ranganathan, N. Krishna, V.
Copyright Year	2002
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA (Mohanty, S.P.)
Abstract	In this paper, we describe a new datapath scheduling algorithm called DFCS based on the concept of dynamic frequency clocking. In dynamic frequency clocking scheme, all functional units in the datapath are driven by a single clock line that switches frequency dynamically at run time. The algorithm schedules lower frequency operators at earlier steps and delays higher frequency operators to later steps. Next, it regroups some of the higher frequency operators with low frequency operators so as to meet the time constraint. During this phase, DFCS assigns the frequency for each cycle and the functional unit with the corresponding voltage. The algorithm has been applied to various high level synthesis benchmark circuits under different time constraints. The experimental results show that using three supply voltage levels (5.0 V, 3.3 V, 2.4 V) and time constraints ({1.5, 1.75 and 2.01} * the critical path delay), average energy savings in the range of 46% to 68% is obtained with respect to using a single-frequency and single-voltage scheme.
Sponsorship	IEEE Comput. Soc. Tech. Committee on VLSI
Starting Page	65
Ending Page	70
File Size	280762
Page Count	6
File Format	PDF
ISBN	0769514863
DOI	10.1109/ISVLSI.2002.1016876
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-04-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Dynamic scheduling Frequency Clocks Time factors Scheduling algorithm Digital-to-frequency converters Delay Voltage Switches High level synthesis
Content Type	Text
Resource Type	Article

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