NDLI: Multi-output timed Shannon circuits

Content Provider	IEEE Xplore Digital Library
Author	Thornton, M.A. Drechsler, R. Miller, D.M.
Copyright Year	2002
Description	Author affiliation: Mississippi State Univ., MS, USA (Thornton, M.A.)
Abstract	Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be reduced. An improvement in the application of this principle for multi-output circuits is presented. Techniques that trade area for power reduction and a method for minimizing the overall circuit switching probability are also included. Experimental results are given and analyzed for these techniques.
Sponsorship	IEEE Comput. Soc. Tech. Committee on VLSI
Starting Page	47
Ending Page	52
File Size	281810
Page Count	6
File Format	PDF
ISBN	0769514863
DOI	10.1109/ISVLSI.2002.1016873
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-04-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Binary decision diagrams Switching circuits Circuit synthesis Power dissipation Boolean functions Minimization methods Logic circuits Data structures Cost function Signal mapping
Content Type	Text
Resource Type	Article

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Multi-output timed Shannon circuits