NDLI: Partial scan testing with single clock control

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2015 IEEE 33rd VLSI Test Symposium (VTS)

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Proceedings of IEEE VLSI Test Symposium

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium

Contactless characterization of microwave integrated circuits by device internal indirect electro-optic probing

On CMOS bridge fault modeling and test pattern evaluation

Classification of bridging faults in CMOS circuits: experimental results and implications for test

Fault injection scan design for enhanced VLSI design verification

Computer-aided failure analysis of VLSI circuits using I/sub DDQ/ testing

The effect of defect clustering on test transparency and defect levels

Carafe: an inductive fault analysis tool for CMOS VLSI circuits

Explorations of sequential ATPG using Boolean satisfiability

CCSTG: an efficient test pattern generator for sequential circuits

Parallelization methods for circuit partitioning based parallel automatic test pattern generation

Finitely self-checking circuits and their application on current sensors

On the check base selection problem for fast adders

Error detection, fault location and reconfiguration for 2D mesh processing element arrays for digital signal processing

Input and output encoding techniques for on-line error detection in combinational logic circuits

An IEEE 1149.1 based voltmeter/oscilloscope in a chip

Quiescent current estimation based on quality requirements

Simulation and generation of I/sub DDQ/ tests for bridging faults in combinational circuits

Analysis of redundant structures in combinational circuits

Minimal hardware multiple signature analysis for BIST

A new built-in self-test method based on prestored testing

A distributed BIST control scheme for complex VLSI devices

Digest of Papers. Eleventh Annual 1993 IEEE VLSI Test Symposium (Cat. No.93TH0537-1)

A neural inverse function for automatic test pattern generation using strictly digital neural networks

Automatic synthesis of DUT board circuits for testing of mixed signal ICs

Hard faults diagnosis in analog circuits using sensitivity analysis

Improvement of analog circuit fault detectability using fault detection observers

LFSROM an algorithm for automatic design synthesis of hardware test pattern generator

LFSR based deterministic hardware for at-speed BIST

Signal probability calculations using partial functional manipulation

Worst-case analysis for pseudorandom testing

Degrading fault model for WSI interconnection lines

Testability of one dimensional ILAs under multiple faults

Concurrent error correction in iterative circuits by recomputing with partitioning and voting

ECC design of a custom DRAM storage unit

Design SRAMs for burn-in

Defect-tolerant cache memory design

Controllability and observability measures for functional-level testability evaluation

Revisiting shift register realization for ease of test generation and testing

On the design for testability of sequential circuits

Testability analysis based on structural and behavioral information

Testability preserving Boolean transforms for logic synthesis

Generation of testable designs from behavioral descriptions using high level synthesis tools

Incremental test pattern generation

Combinational circuit ATPG using binary decision diagrams

Aliasing-free error detection (ALFRED)

Time and space correlated errors in signature analysis

Aliasing computation using fault simulation with fault dropping

On the maximum value of aliasing probabilities for single input signature registers

Physical design for testability for bridges in CMOS circuits

Testable design for BiCMOS stuck-open fault detection

On diagnosis of faults in a scan-chain

Impact of high level functional constraints on testability

Partial scan testing with single clock control

Estimation of reject ratio in testing of combinatorial circuits

Functional verification and simulation of FSM networks

A structured design for test methodology

A model for testing reliable VLSI routing architectures

On parallel switch level fault simulation

Evaluation of test generation algorithms

Simulation of non-classical faults on the gate level-fault modeling

Sensitivity analysis of a radiation immune CMOS logic family under defect conditions

Pattern generator card, emulation, and debug

Digest of Papers. 1992 IEEE VLSI Test Symposium

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

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