NDLI: Combination of structural and state analysis for partial scan

Content Provider	IEEE Xplore Digital Library
Author	Sharma, S. Hsiao, M.S.
Copyright Year	2001
Description	Author affiliation: Intel Corp., Fremont, OR, USA (Sharma, S.)
Abstract	Test generation complexity varies exponentially as the depth of cycles in the S-graph of the circuit. We map the hard-to-reach states obtained from a sequential test generator onto the cycles in the S-graph of the circuit. We then proceed to rank the cycles in terms of the testability gain that would result if the cycle were broken. The primary objective is not to cut all the cycles but to cut those cycles which are preventing the test generator from reaching these hard-to-reach states. To this end, we introduce new measures that combine conventional testability measures such as controllability and observability with the information from hard-to-reach states. We show that this approach overcomes some of the limitations of conventional cycle-cutting. This selective cutting of cycles is shown to yield better results in terms of fault coverage than conventional cycle-cutting.
Sponsorship	Broadcom India
Starting Page	134
Ending Page	139
File Size	558145
Page Count	6
File Format	PDF
ISBN	0769508316
ISSN	10639667
DOI	10.1109/ICVD.2001.902652
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-01-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Flip-flops Sequential analysis Circuit faults Electrical fault detection Fault detection Feedback circuits Automatic testing Controllability Observability
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
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