NDLI: Test vector modification for power reduction during scan testing

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Test vector modification for power reduction during scan testing

Content Provider	IEEE Xplore Digital Library
Author	Kajihara, S. Ishida, K. Miyase, K.
Copyright Year	2002
Description	Author affiliation: Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Japan (Kajihara, S.; Ishida, K.; Miyase, K.)
Abstract	This paper presents a test vector modification method for reducing power dissipation during test application for a full-scan circuit. The method first identifies a set of don't care (X) inputs of given test vectors, to which either logic value 0 or 1 can be assigned without losing fault coverage. Then, the method reassigns logic values to the X inputs so as to decrease switching activity of the circuit during scan shifting. Experimental results for benchmark circuits show the proposed method could decrease switching activity of a given test set to 48% of the original test set.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	160
Ending Page	165
File Size	264872
Page Count	6
File Format	PDF
ISBN	0769515703
DOI	10.1109/VTS.2002.1011128
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-04-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Electronic equipment testing Power dissipation System testing Logic testing Circuit faults Flip-flops Benchmark testing Switching circuits CMOS logic circuits
Content Type	Text
Resource Type	Article

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