NDLI: Test application time reduction for scan circuits using limited scan operations

Content Provider	IEEE Xplore Digital Library
Author	Yonsang Cho Pomeranz, I. Reddy, S.M.
Copyright Year	2004
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA (Yonsang Cho; Pomeranz, I.)
Abstract	We describe a static compaction procedure for full-scan circuits. The procedure accepts a (compact) test set generated for the combinational logic of the circuit and produces a test set with reduced test application time and tester memory, requirements. The reductions are achieved by combining pairs of tests. When a pair of tests is combined, the scan operation required between the two tests is replaced with a limited scan operation. Under a limited scan operation a scan chain of length L is shifted a number of positions S /spl les/ L. As a special case, S = 0 implies that the scan operation between two tests is eliminated altogether. We introduce several techniques to ensure that consideration of test pairs can be done efficiently and results in very high levels of test compaction for benchmark circuits.
Sponsorship	IEEE Electron Devices Soc. IEEE Componants, Packaging and Manufacturing Technol. Soc.
Starting Page	211
Ending Page	216
File Size	321517
Page Count	6
File Format	PDF
ISBN	0769520936
DOI	10.1109/ISQED.2004.1283675
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-03-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Compaction Logic testing Flip-flops Combinational circuits Cities and towns Benchmark testing Costs Circuit faults Sequential analysis
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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