NDLI: MPT-based scheduling for high-level synthesis

Please wait, while we are loading the content...

2015 International Symposium on VLSI Technology, Systems and Applications

Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

Proceedings of Technical Program of 2012 VLSI Technology, System and Application

Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications

Proceedings of 2010 International Symposium on VLSI Technology, System and Application

2009 International Symposium on VLSI Technology, Systems, and Applications

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

2006 International Symposium on VLSI Technology, Systems, and Applications

IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech).

2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672)

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)

Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications

1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers

1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers

Impact of modern ASIC technologies on future telecommunication systems

Integrated circuits through the year 2010

ULSI memory for multimedia applications

Optical lithography techniques for 0.25 /spl mu/m and below: CD control issues

A comparative study of LOCOS-type isolations for 256 Mbit DRAM

Suppressed boron penetration in P/sup +/-poly PMOSFETs with NO-nitrided SiO/sub 2/ gate dielectrics

Process optimization for preventing boron-penetration using P or As co-implant in P-poly gate of P-MOSFETs

Mobility and reliability improvements of fluorinated gate oxide for VLSI technology

Ultra-thin silicon nitride films on Si by jet vapor deposition

Assessment of uniform and non-uniform damage in plasma etched submicron transistors

CAD tools for microprocessor design in the deep submicron era

MPT-based scheduling for high-level synthesis

Finite state machine partitioning for I/O-limited design

One-phase technology mapping for EPGAs using extended GBDD hash tables

Timing and power simulation for deep sub-micron ICs

PLABEK: a complete automatic test pattern generation system for break faults in programmable logic arrays

Stress testing of combinational VLSI circuits using existing test sets

On-chip decoupling capacitor optimization for high-performance VLSI design

Trajectory split method for Monte Carlo simulation of ion implantation demonstrated by three-dimensional poly-buffered LOCOS field oxide corners

Layout-based 3D solid modeling for IC

Efficient and innovative use of three-dimensional geometry services in IC topography and process flow simulations

A novel approach in modeling the diffusion of ion-implanted species during annealing

Two dimensional submicron MOSFET simulation using generalized expansion method and fixed point iteration technique to the Boltzmann transport equation

A consistent gate and substrate current model for submicron MOSFET's by considering energy transport

Field emission displays

Design and implementation of a 525 mm/sup 2/ CMOS digital micromirror device (DMD) display chip

Features of SOI-LSI for low voltage operation

Suppression of geometric component of charge-pumping current in SOI/MOSFETs

A closed-form physical back-gate-bias dependent quasi-saturation model for SOI lateral DMOS devices with self-heating for circuit simulation

Weak avalanche model for SOI and cryogenic analog circuits

Channel doping engineering of MOSFET with adaptable threshold voltage using body effect for low voltage and low power applications

Implementation of low-dielectric-constant materials for ULSI circuit performance improvement

Characterization of electron cyclotron resonance plasma oxide for sub-half micron technology

Effects of PECVD oxide process in the sandwiched SOG structure on MOSFET hot-carrier reliability

Thermal treatment and underlayer effects on silane and dichlorosilane based tungsten silicide for deep sub-micron interconnection processes

Performance and characterization of a highly selective oxide etch for sub-half micron contacts and vias

The study of diffusion barrier layer TiN in Cu/TiN/TiSi/sub 2//Si contact system

Investigation of wafer level reliability of amorphous Si antifuses for high density FPGAs

SVP: scan-line video processor-general purpose video processor

On the bus arbitration for MPEG 2 video decoder

Design and VLSI implementation of MPEG audio decoder

A single-chip lossless data compressor

An image resizing IC for multiple window display

A VLSI architecture for radix-2/sup k/ Viterbi decoding with transpose algorithm

A CAM-based header translation and traffic control chip for ATM systems

On-chip multiprocessor design

Characterization and design of a low-power, high-performance cache architecture

On instruction and data prefetch mechanisms

Delay analysis of micropipelines

A pipelined fuzzy reasoning processor and its software development system

A bidirectional vector associative memory architecture with application to neural networks

Si-MOSFET scaling down to deep-sub-0.1-micron range and future of silicon LSI

A high performance deep submicron MOSFET structure with self-aligned selectively grown W-gate (SAW)

Impact of process-induced damage on MOSFET reliability and suppression of damage by the use of NO-based oxynitride gate dielectrics

Low voltage hot carrier effects and stress methodology

Influence of submicron LDD-MOSFET charge effect on low power circuits

Optimization of lightly-doped-drain (LDD) structure for sub-quarter-/spl mu/m devices using statistical design and response surface methodology

Interface trap induced drain leakage current in various n-MOSFET structures

DRAM technology trend

Lithography technology development and design rule consideration for 0.4-0.35 /spl mu/m DRAM semiconductor processes

Diagonal MOSFETs characterization for 256M DRAM and beyond

Characterization and improvements of flash EEPROM endurance performance by integrating optimized process modules in advanced flash technology

A new observation on initial charge loss in EPROM

A new source-side erase algorithm to reduce disturb problem in flash EPROM

A new erase VT distribution model for reliability design in high density flash EEPROM

CAD for low power: status and promising directions

Charge-delay (Qt) as a performance metric for low-power CMOS circuit design

Pass-transistor dual value logic for low-power CMOS

Design of pipelined FIR filter with MSB-first multiplier

Clocking PLL solutions for high speed computer

Effects of stress-induced mismatches on CMOS analog circuits

Overlap clocking technique for 10 bit 50 MHz 3 V D/A converter

Switched current sigma-delta modulators

1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers

1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers

International Symposium on VLSI Technology, Systems and Applications,

MPT-based scheduling for high-level synthesis

Content Provider	IEEE Xplore Digital Library
Author	Pei-Yung Hsiao Guang-Min Wu Min-Huang Ho Chi-Jeng Chang
Copyright Year	1995
Description	Author affiliation: Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan (Pei-Yung Hsiao; Guang-Min Wu)
Abstract	The conventional scheduling algorithms either give a nonoptimal solution or present a long execution time in moderate cases. In this paper, we propose a branch-and-bound algorithm based on an MPT graph to solve the scheduling problem of high-level synthesis. Six efficient priority rules were developed as bound functions of the algorithm. Experimental results show that this algorithm can obtain a competitive schedule in a very short execution time.
Starting Page	63
Ending Page	67
File Size	373034
Page Count	5
File Format	PDF
ISBN	078032773X
DOI	10.1109/VTSA.1995.524635
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-05-31
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High level synthesis Optimal scheduling Job shop scheduling Scheduling algorithm Processor scheduling Costs Information science Computer industry Computer science education Contracts
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: ndl-support@iitkgp.ac.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in