NDLI: Manufacturability

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Fifteenth International Symposium on Quality Electronic Design

International Symposium on Quality Electronic Design (ISQED)

Thirteenth International Symposium on Quality Electronic Design (ISQED)

2011 12th International Symposium on Quality Electronic Design

2010 11th International Symposium on Quality Electronic Design (ISQED)

2009 10th International Symposium on Quality Electronic Design

9th International Symposium on Quality Electronic Design (isqed 2008)

8th International Symposium on Quality Electronic Design (ISQED'07)

7th International Symposium on Quality Electronic Design (ISQED'06)

Sixth international symposium on quality electronic design (isqed'05)

International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720)

Proceedings. 5th International Symposium on Quality Electronic Design

5th International Symposium on Quality Electronic Design Table of contents

Steering/advisory committee

Technical subcommittees

Conference at a glance

Nanometer-scale CMOS devices

Interconnect modeling

Coping with uncertainty

Manufacturability

Low-power design

Evening panel discussion

Simplify: enable quality,enable innovation

Design for manufacturing? design for yield!!!

Why nano technology? Why now? And what might its impact on electronics

Calligrapher: a new layout migration engine based on geometric closeness

Methodology for automated layout migration for 90nm Itanium/spl reg/2 processor design

Automatic generation of standard cell library in VDSM technologies

A non-charge-sheet based analytical model of undoped symmetric double-gate MOSFETs using SPP approach

Leakage increase of narrow and short BCPMOS

SRAM leakage suppression by minimizing standby supply voltage

Transient analysis of on-chip power distribution networks using equivalent circuit modeling

Leveraging delay slack in flip-flop and buffer insertion for power reduction

Moment computations of nonuniform distributed coupled RLC trees with applications to estimating crosstalk noise

New test access for high resolution /spl Sigma//spl Delta/ ADCs by using the noise transfer function evaluation

Design for testability of FPGA blocks

New challenges emerging on the design of VLSI circuits made of MOSFETs using new gate dielectric materials

Simultaneous multiple-V/sub dd/ scheduling and allocation for partitioned floorplan

Node voltage dependent subthreshold leakage current characteristics of dynamic circuits

Automated formal verification of scheduling process using finite state machines with datapath (FSMD)

Transistor level budgeting for power optimization

Resistance matrix in crosstalk modeling for multiconductor systems

Low power 260k color TFT LCD one-chip driver IC

Analysis and reduction of on-chip inductance effects in power supply grids

A variable reduction technique for the analysis of ultra large-scale power distribution networks

Rewiring for watermarking digital circuits

The IP quality revolution

Layout printability optimization using a silicon simulation methodology

A pattern matching system for linking TCAD and EDA

Shifting methods: adopting a design for manufacture flow

Design tools for packaging

Robustness enhancement through chip-package co-design for high-speed electronics

Flip chip advanced package solder joint embrittlement fault isolation using TDR

A clustering based area I/O planning for flip-chip technology

Low power testing by test vector ordering with vector repetition

Test application time reduction for scan circuits using limited scan operations

Functional vector generation for combinational circuits based on data path coverage metric and mixed integer linear programming

Physically-based simulation of electromigration induced failures in copper dual-damascene interconnect

A methodology for chip-level electromigration risk assessment and product qualification

Circuit level reliability analysis of Cu interconnects

Modeling and simulation of circuit-electromagnetic effects in electronic design flow

A divide-and-conquer algorithm for 3D capacitance extraction [IC modeling]

A comprehensive analytical capacitance model of a two dimensional nanodot array [cellular neural net application]

Interconnect mode conversion in high-speed VLSI circuits

Efficient capacitance extraction for periodic structures by Shanks transformation [IC modeling]

PARADE: parametric delay evaluation under process variation [IC modeling]

Substrate coupling: modeling, simulation and design perspectives

An overview of substrate noise reduction techniques

Supply and substrate noise tolerance using dynamic tracking clusters in configurable memory designs

Modeling of wave behavior of substrate noise coupling for mixed-signal IC design

Estimating phase-locked loop jitter due to substrate coupling: a cyclostationary approach

IP industry: Nordstrom or K-Mart?

Digitally named world: challenges for new social infrastructures

Designing high quality, scaleable SoC's with heterogeneous components

Performance limitations of devices and interconnects and possible alternatives for nanoelectronics

A sensitivity based approach to analyzing signal delay uncertainty of coupled interconnects

Analytical dynamic time delay model of strongly coupled RLC interconnect lines dependent on switching

A scalable communication-centric SoC interconnect architecture

Application specific worst case corners using response surfaces and statistical models

SPICE-compatible thermal simulation with lumped circuit modeling for thermal reliability analysis based on modeling order reduction

Predicting interconnect uncertainty with a new robust model order reduction method

A high performance SIMD framework for design rule checking on Sony's PlayStation 2 Emotion Engine platform [IC layout]

Exact wiring fault minimization via comprehensive layout synthesis for CMOS logic cells

Buffered clock tree for high quality IC design

Frequency specification testing of analog filters using wavelet transform of dynamic supply current

A versatile high speed bit error rate testing scheme

Automated test generation and test point selection for specification test of analog circuits

Power supply optimization in sub-130 nm leakage dominant technologies

Leakage control techniques for designing robust, low power wide-OR domino logic for sub-130nm CMOS technologies

Low power and high performance circuit techniques for high fan-in dynamic gates

Stacked FSMD: a power efficient micro-architecture for high level synthesis

Low-voltage-triggered PNP devices for ESD protection design in mixed-voltage I/O interface with over-VDD and under-VSS signal levels

Full-chip analysis method of ESD protection network

Design to avoid the over-gate-driven effect on ESD protection circuits in deep-submicron CMOS processes

Post silicon power/performance optimization in the presence of process variations using individual well adaptive body biasing (IWABB)

Concurrent error detection for combinational and sequential logic via output compaction

Cost model analysis of DFT based fault tolerant SOC designs

Managing derivative SoC design projects to better results

IPQ: IP qualification for efficient system design

Delay fault diagnosis using timing information

An adaptive path delay fault diagnosis methodology [logic IC testing]

Scan BIST targeting transition faults using a Markov source

The effect of threshold voltages on the soft error rate [memory and logic circuits]

FinFET SRAM - device and circuit design considerations

High input voltage step-down DC-DC converters for integration in a low voltage CMOS process

A high performance radiation-hard field programmable analog array

The design and analysis of non-uniform down-sized differential distributed amplifiers

An asymmetric SRAM cell to lower gate leakage

Call for papers

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.

Proceedings International Symposium on Quality Electronic Design

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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