NDLI: A deductive neural-logic system

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2015 IEEE International Symposium on Multiple-Valued Logic

2014 IEEE 44th International Symposium on Multiple-Valued Logic

2013 IEEE 43rd International Symposium on Multiple-Valued Logic

2012 IEEE 42nd International Symposium on Multiple-Valued Logic

2011 41st IEEE International Symposium on Multiple-Valued Logic

2010 40th IEEE International Symposium on Multiple-Valued Logic

2009 39th International Symposium on Multiple-Valued Logic

38th International Symposium on Multiple Valued Logic (ismvl 2008)

37th International Symposium on Multiple-Valued Logic (ISMVL'07)

36th International Symposium on Multiple-Valued Logic (ISMVL'06)

35th International Symposium on Multiple-Valued Logic (ISMVL'05)

Proceedings. 34th International Symposium on Multiple-Valued Logic

33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.

Proceedings 32nd IEEE International Symposium on Multiple-Valued Logic

Proceedings 31st IEEE International Symposium on Multiple-Valued Logic

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)

Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)

Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)

Proceedings 1997 27th International Symposium on Multiple- Valued Logic

Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)

Proceedings 25th International Symposium on Multiple-Valued Logic

Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)

[1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic

[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic

High-speed digital circuits for a Josephson computer

A superconducting ternary systolic array processor

Heterojunction bipolar technology for emitter-coupled multiple-valued logic in gigahertz adders and multipliers

Unique folding and hysteresis characteristics of RTD for multi-valued logic and counting applications

Easily testable multiple-valued cellular arrays

Aliasing in multiple-valued test data compaction

A new balanced gate for structural testing

Direct cover MVL minimization with cost-tables

Multiple-valued programmable logic array minimization by simulated annealing

Experiences of parallel processing with direct cover algorithms for multiple-valued logic minimization

Design of a 4-valued digital multiplier using an artificial heterogeneous two-layered neural network

Layered MVL neural networks capable of recognizing translated characters

A deductive neural-logic system

Towards the realization of 4-valued CMOS circuits

Incremental gate: a method to compute minimal cost CCD realizations of MVL functions

The theory of clipping voltage-switches and design of quaternary nMOS circuits

An application of the p-valued input, q-kind-valued output logic to the synthesis of the p-valued logical networks

On the efficient decoding of Reed-Solomon codes based on GMD criterion

Defaults as first-class citizens

On the performance of multivalued integrated circuits: past, present and future

Concurrent checking and unidirectional errors in multiple-valued circuits

Application of fail-safe multiple-valued logic for control of power press

Fault analysis on two-level (K+1)-valued logic circuits

(n+1)-valued modal implicative semilattices

Fuzzifying topological groups based on completely distributive residuated lattice-valued logic. I

Dynamic current-mode multi-valued MOS memory with error correction

Bi-CMOS current mode multiple valued logic circuits with 1.5 V supply voltage

On the synthesis of MVL functions for current-mode CMOS circuits implementation

A current-mode CMOS algorithmic analog-to-quaternary converter circuit

On multiple-valued logic functions monotonic with respect to ambiguity

Fundamental properties of extended Kleene-Stone logic functions

On set-valued functions and Boolean collections

Rectangular algebras

A universal logic machine

Design of a multiple-valued rule-programmable matching VLSI chip for real-time rule-based systems

Set-valued logic networks based on optical wavelength multiplexing

Area-efficient implication circuits for very dense Lukasiewicz logic arrays

Semirigid sets of central relations over a finite domain

Amplification of the functional closure operation

A completeness criterion for semi-affine algebras

Design of a multiple-valued VLSI processor for digital control

Residue arithmetic based multiple-valued VLSI image processor

Parallel hardware algorithms with redundant number representations for multiple-valued arithmetic VLSI

Binary input/ternary output switching circuits designed via the sign transformation

Autocorrelation techniques for multi-bit decoder PLAs

Some remarks on Fourier transform and differential operators for digital functions

Profiles of topics and authors of the international symposium on multiple-valued logic for 1971-1991

Code assignment algorithm for highly parallel multiple-valued combinational circuits

Optimal output assignment and the maximum number of implicants needed to cover the multiple-valued logic functions

On the use of multiple-valued switch-level algebra to analyze binary MOS bridge circuits and dynamic circuits

Fast logic synthesis based upon ternary universal logic module U/sub f/

An automatic adjustment method of backpropagation learning parameters, using fuzzy inference

A meaningful infinite-values switching function-fuzzy threshold function and its application to process control

Inverted pendulum controlled circuit using fuzzy state memory-with voltage mode fuzzy state memory

A proposal of fault-checking fuzzy control

Efficient derivation of Reed-Muller expansions in multiple-valued logic systems

The generalized orthonormal expansion of functions with multiple-valued inputs and some of its applications

Optimization of multiple-valued AND-EXOR expressions using multiple-place decision diagrams

On a logic based on fuzzy modalities

Revision principle for approximate reasoning (based on semantic revising method)

On Yager's aggregation operators

Fuzzy logic and the calculus of fuzzy if-then rules

Proceedings. The Twenty-Second International Symposium on Multiple-Valued Logic (Cat. No.92CH3113-8)

[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic

Proceedings of the Twentieth International Symposium on Multiple-Valued Logic

Proceedings. The Nineteenth International Symposium on Multiple-Valued Logic

[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in