NDLI: A floating-gate-MOS-based multiple-valued associative memory

Content Provider	IEEE Xplore Digital Library
Author	Hanyu, T. Higuchi, T.
Copyright Year	1991
Description	Author affiliation: Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan (Hanyu, T.; Higuchi, T.)
Abstract	A digit-serial, multiple-valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory information is stored in each PE by programming the threshold of the down literal which can be easily implemented using special MOS transistors, called floating-gate MOS transistors. It is demonstrated that the number of interconnections and transistors in the 5-valued associative memory can be reduced to 25% and 53%, respectively, in comparison with the corresponding binary implementation.
Starting Page	24
Ending Page	31
File Size	409552
Page Count	8
File Format	PDF
ISBN	0818621451
DOI	10.1109/ISMVL.1991.130700
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-05-26
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Nonvolatile memory Associative memory Very large scale integration MOS devices Logic devices MOSFETs Information retrieval Circuits Registers Random access memory
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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