NDLI: Reliability of reprogrammable nonvolatile memories

Content Provider	IEEE Xplore Digital Library
Author	Sweetman, D.
Copyright Year	1998
Description	Author affiliation: SST, Sunnyvale, CA, USA (Sweetman, D.)
Abstract	The normal difficulties of reliability modeling, prediction, and verification of integrated circuits are complicated by the reliability requirements and erase/program methods of reprogrammable nonvolatile memories (RNVM). The additional reliability requirements are the endurance and data retention parameters. The erase/program methods involve the generation and application of high voltage signals that can cause various "disturb" phenomena, in conjunction with the normal reliability concerns associated with electric field strength. This paper provides a brief overview of modeling, prediction, and verification methods for RNVM, concentrating on the unique aspects of RNVM. Some reference is made to standard methods, where appropriate. Additional information can be found in standard texts on reliability, CMOS circuitry, the IEEE Floating Gate Standard, various IEEE papers, various JEDEC test methods, and books on nonvolatile memory.
Starting Page	101
Ending Page	108
File Size	680158
Page Count	8
File Format	PDF
ISBN	0780345185
DOI	10.1109/NVMT.1998.723231
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-06-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Nonvolatile memory Integrated circuit reliability Integrated circuit modeling Predictive models Circuit testing Signal generators Voltage Semiconductor device modeling CMOS memory circuits Books
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

On evaluating competing bridge fault models for CMOS ICs

Reprogrammable nonvolatile semiconductor memories

On matching properties and process factors for submicrometer CMOS

Designing Reliable SOI CMOS Circuits with Floating-Body Effects

Evaluation of epi layer resistivity effects in mixed-signal submicron CMOS integrated circuits

Modeling of Heavy Ion Induced Charge Loss Mechanisms in Nanocrystal Memory Cells

Qualifying ICs for space environments with the help of parameters modeling

Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories

Variable supply voltage testing for analogue CMOS and bipolar circuits

Reliability of reprogrammable nonvolatile memories

Similar Documents

On evaluating competing bridge fault models for CMOS ICs

Reprogrammable nonvolatile semiconductor memories

On matching properties and process factors for submicrometer CMOS

Designing Reliable SOI CMOS Circuits with Floating-Body Effects

Evaluation of epi layer resistivity effects in mixed-signal submicron CMOS integrated circuits

Modeling of Heavy Ion Induced Charge Loss Mechanisms in Nanocrystal Memory Cells

Qualifying ICs for space environments with the help of parameters modeling

Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories

Variable supply voltage testing for analogue CMOS and bipolar circuits

Reliability of reprogrammable nonvolatile memories