NDLI: A 32k/spl times/8 radiation-hardened CMOS/SONOS EEPROM

Content Provider	IEEE Xplore Digital Library
Author	Williams, D. Bishop, R. Loyd, A. Adams, D. Murray, J. Knoll, M.
Copyright Year	1998
Description	Author affiliation: Northrop Grumman Corp., Baltimore, MD, USA (Williams, D.)
Abstract	A 32k/spl times/8 radiation tolerant CMOS/SONOS EEPROM is described. The technology is a 1.2 micrometer radiation tolerant CMOS process into which is incorporated an oxide-nitride-oxide nonvolatile memory dielectric. This ONO dielectric, when used as the gate dielectric of an n-channel MOSFET, forms the variable threshold transistor which is the basis for the EEPROM. Charge is stored by tunneling into traps in the nitride, rather than on a floating gate as is done with most EEPROMs. No hot electron effects are used for programming or erase, so programming and erase power dissipation are quite low. The circuit was designed at Sandia National Labs and the device was fabricated by Northrop Grumman Corporation.
Starting Page	20
Ending Page	21
File Size	557286
Page Count	2
File Format	PDF
ISBN	0780345185
DOI	10.1109/NVMT.1998.723209
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-06-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SONOS devices EPROM Dielectrics Nonvolatile memory CMOS technology CMOS process MOSFET circuits Tunneling Electron traps Power dissipation
Content Type	Text
Resource Type	Article

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A 32k/spl times/8 radiation-hardened CMOS/SONOS EEPROM