NDLI: Discrete event system specification, synthesis, and optimization of low-power FPGA-based embedded systems

Content Provider	IEEE Xplore Digital Library
Author	Plier, T. Schwartz, D. Lysecky, R. Chungman Seo Zeigler, B.P.
Copyright Year	2013
Description	Author affiliation: Univ. of Arizona, Tucson, AZ, USA (Plier, T.; Schwartz, D.; Lysecky, R.) \|\| RTSync Corp., Sierra Vista, AZ, USA (Chungman Seo; Zeigler, B.P.)
Abstract	Discrete event system specification (DEVS) has been widely used within modeling and simulation to design, verify, and implement complex reactive systems. DEVS provides a robust formalism for designing systems using event-driven, state-based models in which timing information is explicitly defined. In this paper, we present an overview of a DEVS-based hardware design, synthesis, and optimization methodology. Within this approach, hardware DEVS (HDEVS) specifications can be synthesized to hardware, during which the event-driven model and explicit timing allow for an efficient hardware realization using globally asynchronous, locally synchronous design approach. Additionally, we present an optimization method for reducing power consumption through optimal frequency mapping and clock gating of individual components while ensuring system latency constraints are achieved. We further demonstrate the resulting power consumption savings for activity-driven forest fire and asthma health management applications targeting two low-power FPGA devices.
Starting Page	98
Ending Page	105
File Size	1267600
Page Count	8
File Format	PDF
e-ISBN	9781479921980
DOI	10.1109/FPT.2013.6718337
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-09
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Atomic clocks Hardware Computational modeling Analytical models Real-time systems Optimization power optimization modeling and simulation high-level synthesis discrete event system specification (DEVS)
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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