NDLI: Ph.D. forum [breaker page]

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2015 International Conference on Field Programmable Technology (FPT)

2013 International Conference on Field-Programmable Technology (FPT)

Message from the general chair and program co-chairs

Keynote lectures [breaker page]

Recent advances in die stacking and 3D FPGA

Reconfigurable chip advantage compared with GPGPU from the compiler perspective

Why Put FPGAs in your CPU socket?

1.1 Best paper candidate session

Accelerating validation of time-triggered automotive systems on FPGAs

Exploiting partially defective LUTs: Why you don't need perfect fabrication

Maximum flow algorithms for maximum observability during FPGA debug

The architecture and placement algorithm for a uni-directional routing based 3D FPGA

1.2 Architecture

COFFE: Fully-automated transistor sizing for FPGAs

A case for hardened multiplexers in FPGAs

Debugging processors with advanced features by reprogramming LUTs on FPGA

1.3 FPGA applications I

Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities

Accelerating iterative algorithms with asynchronous accumulative updates on FPGAs

High throughput, tree automata based XML processing using FPGAs

Transparent FPGA based device for SQL DDoS mitigation

1.4 Power-aware and dynamically reconfigurable systems

Discrete event system specification, synthesis, and optimization of low-power FPGA-based embedded systems

Optimizing time and space multiplexed computation in a dynamically reconfigurable processor

2.1 High level synthesis I

SOAP: Structural optimization of arithmetic expressions for high-level synthesis

Making domain-specific hardware synthesis tools cost-efficient

System-level FPGA device driver with high-level synthesis support

Bitwidth-optimized hardware accelerators with software fallback

2.2 FPGA applications II

A low latency kernel recursive least squares processor using FPGA technology

Implementation of high performance hardware architecture of OpenSURF algorithm on FPGA

TROJANUS: An ultra-lightweight side-channel leakage generator for FPGAs

Real-time and low power embedded ℓ1-optimization solver design

2.3 (Special Session) Coarse grain reconfigurable architectures for graphics

Efficient execution of augmented reality applications on mobile programmable accelerators

An OpenCL optimizing compiler for reconfigurable processors

Real-time ray tracing on coarse-grained reconfigurable processor

Mobile GPU shader processor based on non-blocking Coarse Grained Reconfigurable Arrays architecture

3.1 High performance computing

Acceleration of real-time Proximity Query for dynamic active constraints

Dynamic Stencil: Effective exploitation of run-time resources in reconfigurable clusters

FlexGrip: A soft GPGPU for FPGAs

3.2 Physical level EDA

Maximizing speed and density of tiled FPGA overlays via partitioning

Improving clock-rate of hard-macro designs

Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting

Automated multi-device placement, I/O voltage supply assignment, and pin assignment in circuit board design

3.3 High level synthesis II

From software threads to parallel hardware in high-level synthesis for FPGAs

StML: Bridging the gap between FPGA design and HDL circuit description

Derivation of efficient FSM from loop nests

An automated flow for the High Level Synthesis of coarse grained parallel applications

Poster session I [breaker page]

A high-throughput FPGA architecture for parallel connected components analysis based on label reuse

Teaching FPGA security

Fast Boolean matching based on NPN classification

Multi-personality partitioning for heterogeneous systems

A hardware acceleration of a phylogenetic tree reconstruction with maximum parsimony algorithm using FPGA

Application-specific customisation of market data feed arbitration

A connection-based router for FPGAs

Flexible hierarchy ray tracing on FPGAs

Design and optimization of heterogeneous tree-based FPGA using 3D technology

NFA reduction for regular expressions matching using FPGA

Runtime hardware/software task transition scheduling for data-adaptable embedded systems

A speculative gather system for Cool Mega-Array

Poster session II [breaker page]

An acceleration method of short read mapping using FPGA

Quantum FPGA architecture design

Real-time high-quality stereo vision system in FPGA

High-level synthesis of dynamic data structures: A case study using Vivado HLS

Datapath fault tolerance for parallel accelerators

Hardware acceleration of biomedical models with OpenCMISS and CellML

sAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface

A 66.1 Gbps single-pipeline AES on FPGA

Partially reconfigurable flux calculation scheme in advection term computation

FPGA-accelerated key search for cold-boot attacks against AES

A low power reconfigurable accelerator using a back-gate bias control technique

Adaptive compression for instruction code of Coarse Grained Reconfigurable Architectures

A non-intrusive portable fault injection framework to assess reliability of FPGA-based designs

Poster session III [breaker page]

High-order reconfigurable FIR filter design based on statistical analysis of CSD coefficients

Color configuration method for an optically reconfigurable gate array

Revisiting the reduction circuit: A case study for simultaneous architecture and precision optimisation

EasyPR — An easy usable open-source PR system

A hardware implementation of Bag of Words and Simhash for image recognition

An FPGA-cluster-accelerated match engine for content-based image retrieval

Spatio-Temporally-Shared Reconfigurable Fast Fourier Transform architecture design

A high-speed FFT based on a six-step algorithm: Applied to a radio telescope for a solar radio burst

A defect-tolerant cluster in a mesh SRAM-based FPGA

Reconfigurable filtered acceleration of short read alignment

Efficient methods for out-of-order load/store execution for high-performance soft processors

Semantics-directed machine architecture in ReWire

ZCluster: A Zynq-based Hadoop cluster

Demo session [breaker page]

An open-source SATA core for Virtex-4 FPGAs

Direct virtual memory access from FPGA for high-productivity heterogeneous computing

Testing reliability techniques for SoCs with fault tolerant CGRA by using live FPGA fault injection

Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing

Enhancing communication on automotive networks using data layer extensions

A prototyping system for hardware distributed objects with diversity of programming languages design and preliminary evaluation

Ph.D. forum [breaker page]

Fast simulation of Digital Spiking Silicon Neuron model employing reconfigurable dataflow computing

Hardware acceleration for the banded Smith-Waterman algorithm with the cycled systolic array

Design competition papers [breaker page]

Implementation of a highly scalable blokus duo solver on FPGA

From C to Blokus Duo with LegUp high-level synthesis

The Liquid Metal Blokus Duo Design

FPGA Blokus Duo Solver using a massively parallel architecture

Artificial intelligence of Blokus Duo on FPGA using Cyber Work Bench

An FPGA-based specific processor for Blokus Duo

An implementation of Blokus Duo player on FPGA

Correction paper [breaker page]

Correction to “Graph Minor Approach for Application Mapping on CGRAs”

2012 International Conference on Field-Programmable Technology

2011 International Conference on Field-Programmable Technology

2010 International Conference on Field-Programmable Technology

2009 International Conference on Field-Programmable Technology

2008 International Conference on Field-Programmable Technology

2007 International Conference on Field-Programmable Technology

2006 IEEE International Conference on Field Programmable Technology

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)

Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.

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Sl.	Authority	Responsibilities	Communication Details
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2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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