NDLI: A bus architecture centric configurable processor system

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2015 IEEE Custom Integrated Circuits Conference (CICC)

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Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)

Simulation and modeling of intermodulation distortion in communication circuits

Intermodulation analysis of mixer circuits based on frequency domain relaxation method

Grid selection strategies for time-mapped harmonic balance simulation of circuits with rapid transitions

Automated macromodelling of "nonlinear" wireless blocks

A frequency-domain, Volterra series-based behavioral simulation tool for RF systems

A fully synthesizable parameterized Viterbi decoder

Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioning

Watermarking-based copyright protection of sequential functions

Hierarchical watermarking for protection of DSP filter cores

Multi-project management in real time

Integrated IC design approach based on software engineering paradigm

Beyond 1 GHz [microprocessor design]

A scalable architecture for MPEG-4 embedded zero tree coding

A MPEG4 programmable codec DSP with an embedded pre/post-processing engine

A low-power single-chip MPEG-2 CODEC LSI

Embedding DRAM in single chip MPEG1 codec LSI

The changing landscape of system-on-a-chip design

Intellectual property re-use and system emulation the keys to succeed the SoC challenge: a digital TV application

A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores

An analog record, playback and processing system on a chip for mobile communications devices

Single GSM mixed signal superchip with 96k bytes FLASH and low power micro-controller

CMOS pipelined ADC employing dither to improve linearity

A 55-mW, 10-bit, 10 Msample/s Nyquist rate CMOS ADC

An 8-bit 150-MHz CMOS A/D converter

A 3.3 V single-poly CMOS audio ADC delta-sigma modulator with 98 dB peak SINAD

A spurious-free delta-sigma DAC using rotated data weighted averaging

A bandpass sigma-delta modulator IC with digital branch-mismatch correction

A 2.7 V 11.8 mW baseband ADC with 72 dB dynamic range for GSM applications

A low-triggering circuitry for dual-direction ESD protection

New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's

Test chips for die stress characterization using arrays of CMOS sensors

Digital detection of parametric faults in data converters

Testing analog circuits by supply voltage variation and supply current monitoring

TRANSPARENT: a system for RTL testability analysis, DFT guidance and hierarchical test generation

Simplifying in-system programming: evolving standards for ISP

Circuit design, transistor sizing and wire layout of FPGA interconnect

A next generation architecture optimized for high density system level integration

A fast, predictable FPGA with PLLs, dual port SRAMs and active repeaters

A field programmable system chip which combines FPGA and ASIC circuitry

A 4.9 ns, 3.3 volt, 512 macrocell, CMOS PLD with hot socket protection and fast in system programming

Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs

RF transmitter architectures and circuits

A 4-dB NF GPS receiver front-end with AGC and 2-b A/D

Mixed-signal quadrature demodulator with a multi-carrier regeneration system

An ultralow power single-chip CMOS 900 MHz receiver for wireless paging

A 5.2 GHz 3.3 V I/Q SiGe RF transceiver

A Si/SiGe HBT timing generator IC for high-bandwidth impulse radio applications

Converting an SRAM from bulk Si to partially depleted SOI

Multiple twisted data line techniques for coupling noise reduction in embedded DRAMs

A 1.8 V, 2.0 ns cycle, 32 KB embedded memory with interleaved castout/reload

A self-timed, fully-parallel content addressable queue for switching applications

A 1.4 V 60 MHz access, 0.25 /spl mu/m embedded flash EEPROM

Analog sense amplifiers for high density NOR flash memories

A CMOS mixed-signal 100 Mb/s receive architecture for fast Ethernet

A dual-speed 125 Mbaud/10 Mbaud CMOS transmitter for Fast Ethernet

Clock and data recovery for 1.25 Gb/s Ethernet transceiver in 0.35 /spl mu/m CMOS

A 1.25 GHz 0.35 /spl mu/m monolithic CMOS PLL clock generator for data communications

A 3 V-CMOS low distortion class AB line driver suitable for HDSL applications

A 2.5-Gb/s one-chip receiver module for gigabit-to-the-home (GTTH) system

Design considerations for distributed microsensor systems

A single chip CMOS APS camera with direct frame difference output

Band runlength coding for low-power continuous micro-monitors

A data-driven micropipeline structure using DSDCVSL

A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells

A /spl plusmn/25 ps jitter 1.9 V CMOS PLL for UltraSPARC microprocessor

Hard disk drive read channels: technology and trends

A 450 Mbit/s EPR4 PRML read/write channel

A CMOS two-path tree search detector

A 110 MHz 350 mW 0.6 /spl mu/ CMOS 16-state generalized-target Viterbi detector for disk drive read channels

A BiCMOS preamplifier/write-driver IC for tape drive

A BiCMOS 1/spl times/ to 5/spl times/ combined analog frontend IC for DVD-ROM and movie players

Device and circuit design issues in SOI technology

The first copper ASICs: A 12M-gate technology

Wireless communication integrated circuits with CMOS-compatible SiGe HBT technology modules

Pre-silicon parameter generation methodology using BSIM3 for device/circuit concurrent design

Substrate-induced high-frequency noise in deep sub-micron MOSFETs for RF applications

RF simulations and physics of the channel noise parameters within MOS transistors

Oscillator phase noise: a tutorial

Noise analysis of a VCO with automatic amplitude control

Modeling and simulation of noise in analog/mixed-signal communication systems

IP reuse creation for system-on-a-chip design

O/sub w/L: An interface description language for IP reuse

A new method for reuse-driven design of digital circuits

An integrated environment for configurable designs

IP repository, a Web based IP reuse infrastructure

The challenge of designing global signals in UDSM CMOS

Clock verification in the presence of IR-drop in the power distribution network

Characterization and modeling of clock skew with process variations

Including inductive effects in interconnect timing analysis

Return-limited inductances: a practical approach to on-chip inductance extraction

An efficient inductance modeling for on-chip interconnects

Mesh-structured on-chip power/ground: design for minimum inductance and characterization for fast R, L extraction

Power supply noise in future IC's: a crystal ball reading

Switching well noise analysis and minimization strategy for low V/sub th/ CMOS integrated circuits

Substrate cross talk noise characterization and prevention in 0.35 /spl mu/m CMOS technology

Substrate injection and crosstalk in CMOS circuits

A methodology for measurement and characterization of substrate noise in high frequency circuits

A review of substrate coupling issues and modeling strategies

A wideband tunable CMOS channel-select filter for a low-IF wireless receiver

A 1 V 5/sup th/-order Bessel filter dedicated to digital standard processes

A 2 V/sub pp/ linear input-range fully balanced CMOS transconductor and its application to a 2.5 V 2.5 MHz Gm-C LPF

A 2.125 Gbaud 1.6 k/spl Omega/ transimpedance preamplifier in 0.5 /spl mu/m CMOS

A 5 GHz, 1 mW CMOS voltage controlled differential injection locked frequency divider

A 3.25 Gb/s injection locked CMOS clock recovery cell

A novel high precision adjustment method for the transconductance of a MOSFET

A new generation of DSP architectures

A single-chip 1.6 billion 16-b MAC/s multiprocessor DSP

A DSP Reed-Solomon coder

Versatile beamforming ASIC architecture for broadband fixed wireless access

A single-chip narrowband frequency domain excisor for a Global Positioning System (GPS) receiver

470 MHz digital filter on delta-sigma modulated signals

Wave pipelining YADDs-a feasibility study

Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs

ANACONDA: robust synthesis of analog circuits via stochastic pattern search

Circuit partitioning by quadratic Boolean programming for reconfigurable circuit boards

Measurements and analyses of substrate noise waveform in mixed signal IC environment

An extended bipolar transistor model for substrate crosstalk analysis

Substrate network modeling for CMOS RF circuit simulation

Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systems

A low-power direct digital frequency synthesizer architecture for wireless communications

A low-power and low-noise CMOS prescaler for 900 MHz to 1.9 GHz wireless applications

Giga bit per second per pin differential CMOS circuits for pseudo ECL signaling

A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution

Frequency scalable non-linear waveform generator for mixed-signal power-factor-correction IC controller

A 1.5 GHz, sub-2 mW CMOS dual-modulus prescaler

VSIA technical challenges

An efficient bus architecture for system-on-chip design

A bus architecture centric configurable processor system

Minimizing the effect of the host bus on the performance of a computational RAM logic-in-memory parallel-processing system

The /spl mu/PP ASIC: design, methodologies and tools for a pay phone system-on-a-chip based on an ARM core and design reuse

Design of high-Q varactors for low-power wireless applications using a standard CMOS process

A 1.3 GHz CMOS VCO with 28% frequency tuning

A quarter-micron CMOS, 1 GHz VCO/prescaler-set for very low power applications

Fully integrated low phase-noise PLLs using closed-loop voltage-to-frequency converter architectures

A wideband quadrature LO generator in digital CMOS

A 900-MHz, 0.8-/spl mu/m CMOS low noise amplifier with 1.2-dB noise figure

A 1 V 900 MHz image-reject downconverter in 0.5 /spl mu/m CMOS

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)

Proceedings of CICC 97 - Custom Integrated Circuits Conference

Proceedings of Custom Integrated Circuits Conference

Proceedings of the IEEE 1995 Custom Integrated Circuits Conference

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93

1992 Proceedings of the IEEE Custom Integrated Circuits Conference

Proceedings of the IEEE 1991 Custom Integrated Circuits Conference

IEEE Proceedings of the Custom Integrated Circuits Conference

1989 Proceedings of the IEEE Custom Integrated Circuits Conference

Proceedings of the IEEE 1988 Custom Integrated Circuits Conference

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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