NDLI: Spatial and Temporal Data Path Remapping for Fault-Tolerant Coarse-Grained Reconfigurable Architectures

Content Provider	IEEE Xplore Digital Library
Author	Eisenhardt, S. Kuster, A. Schweizer, T. Kuhn, T. Rosenstiel, W.
Copyright Year	2011
Abstract	In this contribution we apply a novel strategy for partial remapping to significantly enhance the reliability of coarse-grained reconfigurable architectures. If a component of the architecture is affected by a permanent error, it will be deactivated and the architecture is reconfigured to relinquish the concerned resource. This is achieved by spatially moving operations from defective to unused components. If no unused component is available, operations are additionally moved within time domain to free the required resources. In our experiments, we regard the failure of each single component in an array of processing elements. Depending on the resource usage of the application, between 70% and 100% of the defects can be tolerated. In average, the repair of one failure takes 36 seconds, and the clock frequency has to be reduced by just 0.8% to enable the execution of the changed application mapping.
Starting Page	382
Ending Page	388
File Size	379221
Page Count	7
File Format	PDF
ISBN	9781457717130
ISSN	15505774
DOI	10.1109/DFT.2011.7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-03
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Context Registers Routing Arrays Fault tolerance Fault tolerant systems compilation fault tolerance permanent error coarse-grained reconfigurable remapping
Content Type	Text
Resource Type	Article

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