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Content Provider | IEEE Xplore Digital Library |
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Author | Rai, N. Hashempour, H. Xing, Y. Kruseman, B. Hamdioui, S. |
Copyright Year | 2011 |
Abstract | This paper presents a defect extraction methodology for dislocation anomalies in analogue-mixed signal (AMS) Integrated Circuits (ICs). Dislocation defects can cross the PN junction of a transistor/diode and contribute to leakage related failures. The extraction of dislocation defects from layout information is very difficult. We propose a methodology that accepts a schematic (netlist) of the AMS design and generates a list of dislocation defects by identifying the hierarchical net names of each defect. The methodology parses the schematic (netlist) and locates dislocation defects according to pre-determined rules. The cross section of different devices from the design manual of a process technology are studied and the possible dislocation spots related to PN junctions are listed in a rule file. This methodology is applied to five AMS IC products and a considerable amount of simulation time can be saved by truncating the defect list to the extracted dislocation susceptible spots. |
Starting Page | 139 |
Ending Page | 145 |
File Size | 623617 |
Page Count | 7 |
File Format | |
ISBN | 9781457717130 |
ISSN | 15505774 |
DOI | 10.1109/DFT.2011.21 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2011-10-03 |
Publisher Place | Canada |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Manuals Junctions Stress Pins Crystals Transistors Testing Analog Mixed-Signal Testing Dislocation Defects Schematic Defect Extraction Defect Oriented Test |
Content Type | Text |
Resource Type | Article |
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