NDLI: Concurrent error detection in array dividers by alternating input data

Content Provider	IEEE Xplore Digital Library
Author	Wey, C.-L.
Copyright Year	1991
Description	Author affiliation: Dept. of Elect,-. Eng., Michigan State Univ., East Lansing, MI, USA (Wey, C.-L.)
Abstract	Concurrent error detection (CED) schemes utilizing time redundancy can keep chip area and interconnect to a minimum. An efficient time redundancy scheme, RESO, for array dividers has been reported. Under the same cell fault model, an alternated time redundancy CED scheme using an alternating logic (AL) approach is proposed. The key to the detection of faults using the AL approach is determining that at least one input combination exists for which the error does not result in alternating outputs. Results of this study show that the proposed design achieves the same CED capability as RESO implementation yet with a lower area overhead. Due to the simplicity and low area overhead the proposed AL approach will be very attractive for the design of fault-tolerant VLSI-based systems.<>
Starting Page	114
Ending Page	117
File Size	343205
Page Count	4
File Format	PDF
ISBN	0818622709
DOI	10.1109/ICCD.1991.139858
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-10-14
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Redundancy Fault detection Logic Circuit testing Electrical fault detection Combinational circuits Hardware Encoding Content addressable storage
Content Type	Text
Resource Type	Article

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