NDLI: Novel Devices And Circuits

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Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)

Single-chip implementation of a 32-bit microcontroller for motor drive

HiPCrypto: a high-performance VLSI cryptographic chip

Designing a Java microprocessor core using FPGA technology

Development of Mitsubishi precision scale controller

The memory structures of ATLAS I, a high-performance, 16/spl times/16 ATM switch supporting backpressure

Neural ASIC controller for PWM power systems

Analog And Mixed-signal

ASIC Applications [session summary]

Substrate noise in mixed signal circuits: two case studies [CMOS]

PLL center-frequency tuning using floating-gates

A low distortion linear-tunable continuous-time 488 kHz fifth-order Bessel filter

A 10-bit 20-Msample/s ADC for low-power and low-voltage applications

A 10 b 20-Msample/s 28 mW CMOS ADC in ASIC process

A sixth-order CMOS sigma-delta modulator

A nonlinear integrator model used to design a robust 16-bit, 40 kSPS switched capacitor sigma-delta modulator

Design for test [session summary]

Automated synthesis of a multiple-sequence test generator using 2-D LFSR

Integrated scheduling and allocation of high-level test synthesis

Design and test of a CMOS low-power mixed-analog/digital ASIC for radiation detector readout front ends

Current-testable high-frequency CMOS operational amplifiers

Low Power [session summary]

Low-power high-speed 1-V LSI using a 0.25-/spl mu/m MTCMOS/SIMOX technique

Ultra low-voltage current mirrors and pseudo differential pairs

A novel scheduling-based CAD methodology for exploring the design space of ASICs for low power

Design of standard cells used in low-power ASIC's exploiting the multiple-supply-voltage scheme

A low power transregional MOSFET model for complete power-delay analysis of CMOS gigascale integration (GSI)

The improvement of conditional sum adder for low power applications

Low power design for speech codec

A /spl mu/Watt postage stamp PC

Novel Devices And Circuits

Design of a slew rate controlled output buffer

Analysis and experimental results of a CVTL buffer design

Circuit techniques for high-speed and low-power multi-port SRAMs

A new current-mode sense amplifier for low-voltage low-power SRAM

Self-timed refreshing approach for dynamic memories

Threshold voltage roll-off model for low power bulk accumulation MOSFETs

Asic Cad Applications And Algorithms

The challenge of high-performance, deep-submicron design in a turnkey ASIC environment

800 K gates of random logic in four months: discussion on design methodologies based on "IDEFIX" ASIC experience

Implementation and trade-offs of a DCT architecture using high-level synthesis

A proven embedded DRAM compiler for deep submicron logic processes and system-on-a-chip ASIC designs

Dynamic circuit synthesis using the Owens tool set

Architectural level hierarchical power estimation of control units

Incremental routing in FPGAs

Bipartitioning circuits using TABU search

Relaxed partitioning balance constraints in top-down placement

A practical interconnect driven ASIC design procedure

Asic Architectures

A 440 MHz 16 bit counter in CMOS standard cells

Timing optimization for testable convergent tree adders

Efficient high-speed CIC decimation filter

A novel monolithic isolator for a communications network interface IC

Self-tested self-synchronization by a two-phase input port

Reusable Architectures And Intellectual Property

VHDL design of embedded processor cores: the industry-standard microcontroller 8051 and 68HC11

Methodology for process portable hard IP block creation using cell based array architecture

Datapath library reuse in the design of a high performance floating point unit

Modular realization of threshold logic gates for high performance digital signal processing applications

Simulation And Modeling For High Level Design

System level interconnect power modeling

A VHDL-based simulation methodology for estimating switching activity in static CMOS circuits

Cycle-based simulation on loosely-coupled systems

QPSK demodulator using the methodology of automated system-level ASIC design

Digital Sianal Processing And Image Processing

A versatile and scalable MIMD architecture for studio quality motion estimation

A single chip video coding system with embedded DRAM frame memory for stand-alone applications

A flexible pipelined image processor

Digital design of discrete wavelet transform for MPEG-4

A new VLSI-oriented FFT algorithm and implementation

Improved subtractive division algorithm

A customizable DSP for DMT-based ADSL modem

A phase-coherent numerically controlled oscillator based on pipeline architecture

Session Wpi High Performance Circuits

A voltage-regulated static keeper technique for high-performance ASICs

A high speed CMOS buffer for driving large capacitive loads in digital ASICs

Optimum repeater insertion based on a CMOS delay model for on-chip RLC interconnect

Optimizing RC tree delay in high speed ASICs through repeater insertion

Mems/cmos Integration & Image Sensors

Design of integrated systems including MEMS and ASICs

Image sensors in industrial/machine vision applications

CMOS-based sensors and actuators

A temperature compensation subsystem for an IMEMS CMOS pressure sensor

A low noise cryogenic CMOS preamplifier for high critical temperature superconducting IR and FIR sensors

An all CMOS foveal image sensor chip

Tutorial workshops

Core-based Design Of Systems On A Chip

Formal Hardware Verification: A Users' View Summary

Designing Real-Life Applications Using Synopsys Behavioral Compiler

Design Of Integrated Systems Including Mems And Asics

Dsm Interconnect Modeling And Analysis For Performance And Reliability

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit

Proceedings of Eighth International Application Specific Integrated Circuits Conference

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit

Sixth Annual IEEE International ASIC Conference and Exhibit

[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit

[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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