NDLI: 800 K gates of random logic in four months: discussion on design methodologies based on "IDEFIX" ASIC experience

Content Provider	IEEE Xplore Digital Library
Author	Gastaldello, S. Traverso, G. Kase, R.
Copyright Year	1998
Abstract	Reusability of basic building blocks is an important and effective goal in ASIC design: it speeds up the design, it minimizes the overall bug probability, it eases documentation and maintenance of core functions. Nevertheless, this approach means also a "black box" management, requiring some extra efforts in the implementation phase. Alcatel and Toshiba proved a solution to cope with the lack of knowledge and control of re-used blocks. This methodology seems to be effective, especially for million gates designs in deep submicron technologies. This paper discusses a real ASIC design case, where classical issues were combined: tough schedule; large glue logic (800 K netlist gates), with high connectivity; many clock domains (65 clocks), with many interactions; 50% reuse of old building blocks, many from netlist. The proposed flow improves by shortening design time, achieving high synthesis efficiency without usage of time consuming CRWC methodology, achieving high layout efficiency bypassing time consuming (and sometimes misleading) floorplanning /hierarchical methodologies.
Starting Page	187
Ending Page	191
File Size	538521
Page Count	5
File Format	PDF
ISBN	0780349806
ISSN	10630988
DOI	10.1109/ASIC.1998.722894
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-09-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Logic design Design methodology Application specific integrated circuits Clocks Automatic test pattern generation Circuit synthesis Hardware design languages Buildings Research and development
Content Type	Text
Resource Type	Article

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