NDLI: FPGA-based FIR filters using digit-serial arithmetic

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Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

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Index of authors

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Sixth Annual IEEE International ASIC Conference and Exhibit

[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit

[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit

FPGA-based FIR filters using digit-serial arithmetic

Content Provider	IEEE Xplore Digital Library
Author	Hanho Lee Sobelman, G.E.
Copyright Year	1997
Description	Author affiliation: Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA (Hanho Lee)
Abstract	This paper describes the use of digit-serial arithmetic for compact and efficient implementations of real-time DSP applications on field programmable gate arrays (FPGAs). As an example, the implementation of a digit-serial 5-tap FIR filter on a Xilinx XC4010 FPGA is considered. An analysis of the performance comparison of several FIR filters is described. The results show that digit-serial designs with a digit-size of 2 bits have about 17% smaller area-time product than those of a bit-serial implementations.
Starting Page	225
Ending Page	228
File Size	428701
Page Count	4
File Format	PDF
ISBN	0780342836
ISSN	10630988
DOI	10.1109/ASIC.1997.617010
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-09-07
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finite impulse response filter Arithmetic Field programmable gate arrays Digital signal processing Digital filters Low pass filters Routing Throughput Signal processing Nonlinear filters
Content Type	Text
Resource Type	Article

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