NDLI: Pipelined adaptive filters

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Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

Voltage reduction techniques for portable systems

An ultra-low-voltage MTCMOS/SIMOX gate array

Low-voltage high-performance switched current memory cell

A low power high speed error correction code macro using complementary pass transistor logic circuit

Low-voltage floating-gate current mirrors

The power analysis of interconnect structures

Challenges and approaches in mixed signal RF testing

A prototype supply current monitor for testing analogue circuits

An optimal method for testing digital to analog converters

Digital components for built-in self-test of analog circuits

Efficient redundancy identification for test pattern generation

Boundary scan access of built-in self-test for field programmable gate arrays

Boundary scan adaption for active substrate MCM-test

CMOS read-out IC with op-amp pixel amplifier for infrared focal plane arrays

Testable VLSI circuit design of SIMD graphics engine

The implementation of modulator using FPGA technology for W-CDMA WLL

A portable printer controller ASIC design using behavioral compiler

An improved silicon retina chip with optical input and optical output

ASIC for signal processing and control for public telephones

On the relationship among accuracy, tolerance and compensation in the deep sub-micron era

Applying functional decomposition for depth minimal technology mapping of multiplexer based FPGAs

An accurate, computationally efficient crosstalk model for routing high-speed MCMs

Automatic feasibility/performance estimation of mixed-signal circuits based on design specifications

An easy approach to formal verification

Layout verification to improve ESD/latchup immunity of scaled-down CMOS cell libraries

HDL generation from parameterized schematic design system

DSL technology shifts carriers to the passing lane for Internet access

ASIC design for monobit receiver

TU11/TU12 signal frame alignment and supervisory monitoring ASIC design

A 55 MBaud single chip complex adaptive transversal equalizer for digital wireless communication systems

A unique section overhead processor for STM-64

Energy saving techniques for architecture design of portable embedded devices

A robust CMOS logic technique for building high frequency circuits with efficient pipelining

Data dependent precharging dynamic chain architecture for low power end high speed adders

Rapid prototyping of telecommunication systems on mixed HW/SW architectures

Projections for high performance, minimum power CMOS ASIC technologies: 1998-2010

An efficient statistical method to estimate average power in sequential circuits considering input sensitivities

Input reordering for power and delay optimization

Synthesize pass transistor logic gate by using free binary decision diagram

TDD: a technology dependent decomposition algorithm for LUT-based FPGAs

A layout advisor for timing-critical bus routing

Optimal complex operator mapping

Mixed-signal considerations when integrating systems

FPGA-based FIR filters using digit-serial arithmetic

Low power optimization of bit-serial digital filters

VSB demodulator ASIC design and development for HDTV system

A reconfigurable hardware accelerator for moment computation

Pipelined adaptive filters

Synthesis of building blocks for low-power stochastic pulse coded systems

Design and implementation of an object-based video coder chip set based on syntactic pattern recognition

Design issues for flip-chip ICs in multilayer packages

An intrinsic area-array pad router for ICs

I/O impedance matching algorithm for high-performance ASICs

A 5 volt drive output buffer in a 3 volt technology

Process, voltage and temperature compensation of off-chip-driver circuits for sub-0.25-/spl mu/m CMOS technology

ESD protection for CMOS ASIC in noisy environments with high-current low-voltage triggering SCR devices

Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC's with substrate-triggering technique

Lorentz force MOS transistor

Substrate coupling in mixed-mode and RF integrated circuits

A new digital to analog converter resistor string architecture

A MAGFET sensor array for digital magnetic signal reading

LVDS I/O buffers with a controlled reference circuit

Low-power CMOS on-chip voltage reference using MOS PTAT: an EP approach

Test board design and measurement techniques for high-frequency fully-differential CMOS OTAs

Modeling and simulation with hardware description languages

A modern ASIC controller for a 6-pulse rectifier

AHDL models to detect verification problems early in the design process

Computer aided system simulation of micropower CMOS analog hearing aid

Using voltage and temperature adders to account for variations in operating conditions during digital timing simulation

Low voltage and low power design of microwave mixer

A general method to double the cycle simulation speed

Index of authors

Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit

Proceedings of Eighth International Application Specific Integrated Circuits Conference

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit

Sixth Annual IEEE International ASIC Conference and Exhibit

[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit

[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit

Pipelined adaptive filters

Content Provider	IEEE Xplore Digital Library
Author	Langhammer, M.
Copyright Year	1997
Description	Author affiliation: Kaytronics Inc., Mississauga, Ont., Canada (Langhammer, M.)
Abstract	This paper examines methods for the design, implementation, and verification of pipelined adaptive filters in programmable logic. Pipelined adaptive filters can operate at far higher rates than non-pipelined types, but relaxations are required to realize these recursive structures. Design tools that automate the implementation of these filters are demonstrated, along with utilities that allow simulation of the completed system in both fixed and floating point formats. Finally, a communications channel equalization is designed and implemented.
Starting Page	242
Ending Page	245
File Size	356321
Page Count	4
File Format	PDF
ISBN	0780342836
ISSN	10630988
DOI	10.1109/ASIC.1997.617014
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-09-07
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Adaptive filters Delay Finite impulse response filter Pipeline processing Feedback Programmable logic arrays Programmable logic devices Logic arrays Logic design Convergence
Content Type	Text
Resource Type	Article

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