NDLI: FPGA based application specific processing for sensor nodes

Content Provider	IEEE Xplore Digital Library
Author	Nylanden, T. Janhunen, J. Hannuksela, J. Silven, O.
Copyright Year	2011
Description	Author affiliation: Centre for Wireless Communications University of Oulu, Finland (Janhunen, J.) \|\| Computer Science and Engineering Laboratory, University of Oulu, Finland (Nylanden, T.; Hannuksela, J.; Silven, O.)
Abstract	Energy efficient sensor nodes are among the rapidly expanding applications for embedded systems technology. Typically, the processing resources in sensor nodes are based on programmable micro-controllers and digital signal processors, and the same processing architecture is used regardless of the actual task of the node. This regularly results in at least an order of magnitude over-provisioning of resources, and in higher power consumption than would be needed by tightly application specific processing solutions. Currently, experiments show that Flash FPGA technology enables implementing precisely provisioned processing for sensor nodes with energy efficiency that rivals off-the-shelf processor solutions. The expected competitiveness originates from savings in silicon real-estate, and lowered software overheads, as inherently parallel tasks can be offloaded to dedicated hardware accelerators on the same die with a microcontroller unit, and radio baseband. The results pave the way for a novel type of self-powered sensor nodes whose processing resources are configured according to their tasks.
Starting Page	118
Ending Page	123
File Size	1644995
Page Count	6
File Format	PDF
ISBN	9781457708022
e-ISBN	9781457708015
DOI	10.1109/SAMOS.2011.6045452
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-18
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wireless sensor networks Energy consumption Random access memory Computer architecture Cyclones Power dissipation Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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