NDLI: An based-FPGA dynamic power management technique for wireless sensor network

Content Provider	IEEE Xplore Digital Library
Author	Ingles da Silva, A. Dacencio Pereira, F.
Copyright Year	2014
Description	Author affiliation: Comput. & Inf. Syst. Res. Lab, Univ. Center Euripides Marilia (UNIVEM), Marilia, Brazil (Ingles da Silva, A.; Dacencio Pereira, F.)
Abstract	Technologies like FPGA appear with features to be explored as implementation of low-power system. In this project we built a low-power circuit applying the implementation of a technique to minimize the clocks domains of the circuit. The architecture built has all the necessary features to integrate, synchronize and perform communication according to the application. Also a balanced operation mode among performance, reliability in the communication and power consumption for sensor nodes on FPGA is achieved. The architecture described is proposed and evaluated in an eASIC Nextreme-2 architecture, only the full-operation mode is discussed.
Starting Page	189
Ending Page	194
File Size	480583
Page Count	6
File Format	PDF
e-ISBN	9781479931668
DOI	10.1109/ICeND.2014.6991377
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-04-29
Publisher Place	Lebanon
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wireless sensor network Energy consumption Wireless sensor networks Power demand FPGA Receivers Dynamic Power Management Synchronization Low-power Field programmable gate arrays Logical architecture Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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