NDLI: Fail pattern identification for memory built-in self-repair

Content Provider	IEEE Xplore Digital Library
Author	Rei-Fu Huang Chin-Lung Su Cheng-Wen Wu Shen-Tien Lin Kun-Lun Luo Yeong-Jar Chang
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. Eng., National Tsing Hua Univ., Hsinchu, Taiwan (Rei-Fu Huang; Chin-Lung Su; Cheng-Wen Wu)
Abstract	With the advent of deep submicron technology and system-on-chip (SOC) design methodology, we are seeing on-chip memory cores to represent a growing percentage of the chip area. The yield of an SOC is usually dominated by the memory yield, so the improvement of memory yield is crucial in SOC development. In this work, we propose a built-in self-repair (BISR) scheme for memory yield improving. The novelty of our approach is that we can identify the fail patterns so that appropriate spare elements (e.g., spare rows, columns, words, or blocks) can be allocated to repair the defective memory. Some BISR methods are discussed and compared. We select the scheme that uses fewer spare elements than others given the same repair rate. The area overhead of the BISR scheme is only 2.2% for an 8K/spl times/64 memory.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	366
Ending Page	371
File Size	104474
Page Count	6
File Format	PDF
ISBN	0769522351
ISSN	10817735
DOI	10.1109/ATS.2004.43
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-11-15
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Redundancy System-on-a-chip Algorithm design and analysis Partitioning algorithms Hardware Fault diagnosis Design methodology Logic Costs
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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