NDLI: An intra-cell defect grading tool

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2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

Foreword to the $17^{th}$ IEEE DDECS symposium

Symposium committees

Table of contents

Detection & diagnostics in today's advanced technology nodes

Automatic architecture exploration of massively parallel MPSoCs for modern cyber-physical systems

Design and testing of integrated circuit of pixel architecture for fast x-ray imaging applications

SiP design flow and 3D DRC for MEMS

Development of 3D space partitioning and design rule check for smart system solutions

Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs

Automatically connecting hardware blocks via light-weight matching techniques

A double-path intra prediction architecture for the hardware H.265/HEVC encoder

Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic

Quality assurance in memory built-in self-test tools

Generic built-in self-repair architectures for SoC logic cores

A 64-MHz∼640-MHz 64-phase clock generator

A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology

Burst-pulse Generator based on transmission line toward sub-MMW

A 120V high voltage DAC array for a tunable antenna in communication system

Fast time-parallel C-based event-driven RTL simulation

Lower bounds of the size of Shared Structurally Synthesized BDDs

BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching

Analysis of current conveyor non-idealities for implementation as integrator in delta sigma modulators

Multistage low ripple charge pump

A novel impedance calculation method and its time efficiency evaluation

Test-data compression with low number of channels and short test time

Test data compression based on reuse and bit-flipping of parts of dictionary entries

Timing-aware ATPG for critical paths with multiple TSVs

A layout based customized testing technique for total microfluidic operations in digital microfluidic biochips

Optimizing DD-based synthesis of reversible circuits using negative control lines

Evolutionary design of approximate multipliers under different error metrics

Online testing of many-core systems in the Dark Silicon era

Reliable execution of statechart-generated correct embedded software under soft errors

Combining fault tolerance and self repair at minimum cost in power and hardware

Self-managing power management unit

A low supply voltage synchronous mirror delay with quadrature phase output

High throughput architecture for the Advanced Encryption Standard Algorithm

Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA

Low latency book handling in FPGA for high frequency trading

CRC based hashing in FPGA using DSP blocks

The LSI implementation of a memory based field programmable device for MCU peripherals

Design methodology of configurable high performance packet parser for FPGA

A study on fast pipelined pseudo-random number generator based on chaotic logistic map

Modeling timing constraints for automatic generation of embedded test instruments

Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce

Test and diagnosis of power switches

Fast lookup for dynamic packet filtering in FPGA

Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults

Stabilization methods for integrated high voltage charge pumps

FPGA design of the computation unit for the semi-global stereo matching algorithm

System design for enhanced forward-engineering possibilities of safety critical embedded systems

Mismatch effects and their correction in large area ASICs

A unified CMOS inverter model for planar and FinFET nanoscale technologies

A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems

Dedicated hardware architecture for object tracking preprocessing implemented in FPGA

Emulation based fault injection on UHF RFID transponder

Sources of bias in EDA tools and its influence

Automatic and reliable electrical characterization of MOSFETs

An approach towards selection of the oscillation frequency for oscillation test of analog ICs

Customer return detection with features selection

Designing of Test Pattern Generators for stimulation of crosstalk faults in bus-type connections

On NFA-split architecture optimizations

ADCs in deep submicron technologies for ASICs of pixel architecture

Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits

On the in-field test of Branch Prediction Units using the correlated predictor mechanism

FPGA architectures of the quantization and the dequantization for video encoders

An efficient hardware architecture for inter-prediction in H.264/AVC encoders

An intra-cell defect grading tool

Heuristic algorithm of two-level minimization of fuzzy logic functions

Verifying robust frequency domain properties of non linear oscillators using SMT

Modeling and analysis of cracked through silicon via (TSV) interconnections

Case study: BISR for a processor multiplier

Efficient VHDL implementation of symbol synchronization for software radio based on FPGA

TTTC: Test technology technical council

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems

2006 IEEE Design and Diagnostics of Electronic Circuits and systems

An intra-cell defect grading tool

Content Provider	IEEE Xplore Digital Library
Author	Bosio, A. Dilillo, L. Girard, P. Todri-Sanial, A. Virazel, A. Bernabovi, S. Bernardi, P.
Copyright Year	2014
Description	Author affiliation: Politec. di Torino, Turin, Italy (Bernabovi, S.; Bernardi, P.) \|\| LIRMM, Montpellier, France (Bosio, A.; Dilillo, L.; Girard, P.; Todri-Sanial, A.; Virazel, A.)
Abstract	With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.
Sponsorship	IEEE Comput. Soc.
Starting Page	298
Ending Page	301
File Size	273068
Page Count	4
File Format	PDF
ISBN	9781479945603
e-ISBN	9781479945580
DOI	10.1109/DDECS.2014.6868814
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-04-23
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Logic gates Libraries Integrated circuit modeling Dictionaries Databases Automatic test pattern generation fault simulation intra-cell defect test diagnosis
Content Type	Text
Resource Type	Article

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