NDLI: FPGA design of the computation unit for the semi-global stereo matching algorithm

Content Provider	IEEE Xplore Digital Library
Author	Roszkowski, M. Pastuszak, G.
Copyright Year	2014
Description	Author affiliation: Inst. of Radioelectron., Warsaw Univ. of Technol., Warsaw, Poland (Roszkowski, M.; Pastuszak, G.)
Abstract	In recent years, it is possible to observe an increased interest in methods of stereo-vision as they allow simple 3D representations of the scene acquired with two optical cameras. However, not all methods described in literature are suitable for a real-time implementation in hardware. One method generally considered to produce good results and viable for such an implementation is semi-global stereo matching. Nevertheless, there are not many in-depth descriptions of hardware architectures of modules implementing this method in the literature. In this article we try to fill in this gap by presenting a detailed FPGA-oriented architecture of the basic computation unit supporting the semi-global matching algorithm. The unit is responsible for carrying out all calculation necessary to select the best disparity for each pixel. We also present a novel solution to the problem of storing paths' costs for each pixel and discuss the trade-offs between the size of the unit in an FPGA chip and precision of the computed disparity map.
Sponsorship	IEEE Comput. Soc.
Starting Page	230
Ending Page	233
File Size	274392
Page Count	4
File Format	PDF
ISBN	9781479945603
e-ISBN	9781479945580
DOI	10.1109/DDECS.2014.6868796
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-04-23
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Hardware Stereo vision Heuristic algorithms Field programmable gate arrays Clocks Real-time systems
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

FPGA design and implementation of a real-time stereo vision system

FPGA implementation for stereo matching algorithm

Matching cost computation algorithm and high speed FPGA architecture for high quality real-time Semi Global Matching stereo vision for road scenes

Real-Time Stereo Vision Processing System in a FPGA

Post-processing algorithms for real-time active stereo vision

Towards hardware stereoscopic 3D reconstruction a real-time FPGA computation of the disparity map

Constrained sliding window correspondence algorithm for fast stereo vision

FPGA Based Stereo Vision System to Display Disparity Map in Realtime

Dense stereo disparity maps by Dynamic Time Warp with sparse features and FPGA acceleration

FPGA design of the computation unit for the semi-global stereo matching algorithm

Similar Documents

FPGA design and implementation of a real-time stereo vision system

FPGA implementation for stereo matching algorithm

Matching cost computation algorithm and high speed FPGA architecture for high quality real-time Semi Global Matching stereo vision for road scenes

Real-Time Stereo Vision Processing System in a FPGA

Post-processing algorithms for real-time active stereo vision

Towards hardware stereoscopic 3D reconstruction a real-time FPGA computation of the disparity map

Constrained sliding window correspondence algorithm for fast stereo vision

FPGA Based Stereo Vision System to Display Disparity Map in Realtime

Dense stereo disparity maps by Dynamic Time Warp with sparse features and FPGA acceleration

FPGA design of the computation unit for the semi-global stereo matching algorithm