NDLI: Ultra-low leakage MTCMOS circuits with regular-V long channel stacked footers for deep sub-100 nm technologies

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VLSI Design, Automation and Test(VLSI-DAT)

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test

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Proceedings of 2011 International Symposium on VLSI Design, Automation and Test

Proceedings of 2010 International Symposium on VLSI Design, Automation and Test

2009 International Symposium on VLSI Design, Automation and Test

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

2008 international symposium on VLSI design, automation, and test organization

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Table of content

Efficient analog signal processing in nm CMOS technologies

Reasoning about Data: Bits, bit vectors, or words

Logic diagnosis, yield learning and quality of test

Temperature aware SoC design for reduced leakage power and enhanced reliability

A transceiver 10GBase-T in 90nm CMOS

A 1.6–880MHz synthesizable ADPLL in 0.13um CMOS

Increasing the on-die nodal observability and controllability use of advanced design for debug circuit features

An area-efficient design for Programmable memory Built-In Self-Test

Estimation of energy consumed by software in processor caches

On-chip interconnection design and SoC integration with OCP

A scalable and accurate rectilinear Steiner minimal tree algorithm

Obstacle-Avoiding Rectilinear Steiner Minimal Tree construction

On minimizing topography variation in multi-layer oxide CMP manufacturability

A 400-MHz super-regenerative receiver with digital calibration for capsule endoscope systems in 0.18-μm CMOS

A 460MHz∼870MHz CMOS wideband low noise amplifier for DVB-T

A CMOS low-noise amplifier with impedance feedback for ultra-wideband wireless receiver system

Exploiting capacitance in high-performance computer systems

An 8.69 Mvertices/s 278 Mpixels/s tile-based 3d graphics full pipeline with embedded performance counting module, real-time bus tracer and protocol checker for consumer electronics

A power-efficient SRAM core architecture with segmentation-free and rectangular accessibility for super-parallel video processing

Built-in jitter measurement methodology for spread-spectrum clock generators

DfT for full accessibility of multi-step analog to digital converters

Debugging clock-data race failures caused by vulnerable design

Ultra-low leakage MTCMOS circuits with regular-V long channel stacked footers for deep sub-100 nm technologies

A well-structured modified Booth multiplier design

Transistor sizing and layout merging of basic cells in pass transistor logic cell library

1.8 V to 5.0 V mixed-voltage-tolerant I/O buffer with 54.59% output duty cycle

Testing the hold time fault for large industrial design

An improved feature ranking method for diagnosis of systematic timing uncertainty

A systematic methodology to employ error-tolerance for yield improvement

Multiple error diagnosis in large combinational circuits using an efficient parallel vector simulation

A 62–66.1GHz phase-locked loop in 0.13um CMOS technology

A 1.1-V CMOS frequency synthesizer with pass-transistor-logic prescaler for U-NII band system

A clock and data recovery circuit with wide linear range frequency detector

A complementary Colpitts VCO implemented with ring inductor

A hardware/software co-solution to achieving high throughput required by motion estimation part in H.264/AVC HDTV real-time application

Design of a distributed JPEG encoder on a scalable NoC platform

Multilevel communication modeling for Multiprocessor System-on-Chip

Networks-In-Package: Performances management and design methodology

A 330MHz 11 bit 26.4mW CMOS low-hold-pedestal fully differential track-and-hold circuit

A 10-bit 300MHz $0.1mm^{2}$ triple-channel current-steering DAC 75.98dB SFDR in 65nm

A 300MHz, 48mW analog front-end design for IEEE 802.3an 10GBase-T Ethernet

A 93dB-ohm 2.5Gb/s CMOS burst-mode optical receiver with internal reset creation

Synthesis of a timing-error detection architecture

High-level synthesis algorithms with floorplaning for distributed/shared-register architectures

Sensitivity-based multiple-Vt cell swapping for leakage power reduction

A code generation algorithm of crosstalk-avoidance code with memory for low-power on-chip bus

Technology trend of ADCs

New transient detection circuit for system-level ESD protection

Adaptive digital techniques for efficiency and linearity enhancement of CMOS RF power amplifiers

Overview of ITRI PAC project - from VLIW DSP processor to multicore computing platform

An OFDMA-based wireless body area network using frequency pre-calibration

Design of an OFDMA baseband receiver for 3GPP long-term evolution

A 4-PAM adaptive analog equalizer for backplane interconnections

Fully integrated super-regenerative bandpass filters for 3.1-to-7GHz multiband UWB system

A 120-MHz active-RC filter with an agile frequency tuning scheme in 0.18-μm CMOS

A novel miniaturized wide-band Wilkinson power divider employing two-dimensional transmission line

High-throughput 12-mode CTC decoder for WiMAX standard

High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule

A radix-4 soft-output Viterbi architecture

Power efficient low latency survivor memory architecture for Viterbi decoder

A 1-GS/s CMOS 6-bit flash ADC with an offset calibrating method

A precise delay generator circuit using the average delay technique

A 0.35-um CMOS switched-inductor dual-band LC-tank frequency divider

Adaptive biasing circuit overcoming process variation for high-speed circuits in scaled CMOS technology

A 2.4-GHz 0.18-μm CMOS doubly balanced mixer with high linearity

CMOS low-noise amplifier with shunt-peaking load for group 1∼3 MB-OFDM ultra-wideband wireless receiver

A 90nm 10-bit 1GS/s current-steering DAC with 1-V supply voltage

A universal look-ahead algorithm for pipelining IIR filters

A novel low-power processor with variable pipeline control

A high-resolution all-digital phase-locked loop with its application to built-in speed grading for memory

Algorithmic factorisation for low power FPGA implementations through increased data locality

Hardware realization of a medical diagnostic system based on Probabilistic CMOS (PCMOS) technology

Design of a DVB-T/H compliant baseband receiver

Topology generation and floorplanning for low power application-specific Network-on-Chips

Power and density-aware buffer insertion

Impact quantification of the dummy metal fills on nanometer VLSI designs for DFM

A self-testing and calibration technique for current-steering DACs

A feasibility study of on-wafer wireless testing

Phase noise testing of single chip TV tuners

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

2006 International Symposium on VLSI Design, Automation and Test

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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