NDLI: An efficient and low power systolic squarer

Content Provider	IEEE Xplore Digital Library
Author	Yuan-Long Jeang Liang-Bi Chen Jiun-Hau Tu Ing-Jer Huang
Copyright Year	2005
Description	Author affiliation: Dept. of Electron. Eng., National Kaohsiung Univ. of Appl. Sci., Taiwan (Yuan-Long Jeang)
Abstract	Squarer has been extensively applied on image, video and data compression for portable devices. Thus, squarer with faster speed, smaller die size, and lower power is tremendously important practically. By carefully classifying the cells in straightforward systolic array into 5 groups and carefully design each cell by reducing the gate count of full adder and D flip flops, we proposed a new systolic squarer that outperforms the other circuits (Chun-Lung Shu and Wu-Hung Lu, 2003; Kolagotla et al., 1998; Dumonteix et al., 2001) on number of transistors, speed, power, and power/speed ratio. The design has been implemented on chip using TSMC 0.35 /spl mu/m 2P4M process.
Sponsorship	Ind. Technol. Res. Inst., Taiwan
Starting Page	37
Ending Page	40
File Size	601532
Page Count	4
File Format	PDF
ISBN	0780390601
DOI	10.1109/VDAT.2005.1500014
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-04-27
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuits Data engineering Power engineering and energy Data compression Adders Digital signal processing chips Equations Systolic arrays Propagation delay Energy consumption
Content Type	Text
Resource Type	Article

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