NDLI: An efficient VLSI architecture for 2-D convolution with quadrant symmetric kernels

Content Provider	IEEE Xplore Digital Library
Author	Zhang, M.Z. Ngo, H.T. Livingston, A.R. Asari, V.K.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Old Dominion Univ., Norfolk, VA, USA (Zhang, M.Z.; Ngo, H.T.; Livingston, A.R.; Asari, V.K.)
Abstract	A high performance digital architecture for computing 2D convolution utilizing the quadrant symmetry of the kernels is proposed in this paper. Pixels in the four quadrants of the kernel region with respect to an image pixel are considered simultaneously for computing the partial products of the convolution sum. A novel data handling strategy to identify the pixels to be fed to different processing elements helps reducing the data storage requirements in the circuitry. The new design results in 75% reduction in multipliers and 50% reduction in adders when compared with the conventional systolic architecture. The proposed architecture design is capable of performing convolution operations with 14/spl times/14 kernel at a rate of 57 1024/spl times/1024 frames per second in a Xilinx 's Virtex 2v2000ff896-4 FPGA.
Sponsorship	IEEE Comput. Soc. Tech. Comm. on VLSI
Starting Page	303
Ending Page	304
File Size	65840
Page Count	2
File Format	PDF
ISBN	076952365X
DOI	10.1109/ISVLSI.2005.15
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Convolution Kernel Computer architecture Pixel High performance computing Data handling Memory Circuits Adders systolic architecture 2-D convolution symmetric kernel pipelined architecture
Content Type	Text
Resource Type	Article

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