NDLI: Symposium Committees

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2015 IEEE Computer Society Annual Symposium on VLSI

2014 IEEE Computer Society Annual Symposium on VLSI

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

2012 IEEE Computer Society Annual Symposium on VLSI

2011 IEEE Computer Society Annual Symposium on VLSI

2010 IEEE Computer Society Annual Symposium on VLSI

2009 IEEE Computer Society Annual Symposium on VLSI

2008 IEEE Computer Society Annual Symposium on VLSI

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)

IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

Proceedings. IEEE Computer Society Annual Symposium on VLSI

Message From the Technical Program Chair

Symposium Committees

Let's think analog

Analysis of a mask-based nanowire decoder

Bi-direction synthesis for reversible circuits

Boost logic : a high speed energy recovery circuit family

High performance array processor for video decoding

High speed redundant adder and divider in output prediction logic

Sensing design issues in deep submicron CMOS SRAMs

Novel switch block architecture using non-volatile functional pass-gate for multi-context FPGAs

409ps 4.7 FO4 64b adder based on output prediction logic in 0.18um CMOS

Quasi-exact BDD minimization using relaxed best-first search

Two-phase resonant clock distribution

Fast analog circuit synthesis using multiparameter sensitivity analysis based on element-coefficient diagrams

A modified cascaded sigma-delta modulator with improved linearity

Jitter in deep sub-micron interconnect

Exploiting inter-processor data sharing for improving behavior of multi-processor SoCs

eWatch: context sensitive system design case study

A data-driven approach for embedded security

System level methodology for programming CMP based multi-threaded network processor architectures

Multi-grained reconfigurable datapath structures for online-adaptive reconfigurable hardware architectures

A high speed reconfigurable gate array for gigahertz applications

Hardware implementation of an additive bit-serial algorithm for the discrete logarithm modulo 2/sup k/

An improved dynamic optically reconfigurable gate array

Lemma exchange in a microcontroller based parallel SAT solver

Power analysis of rotary clock

On reducing peak current and power during test

Design and implementaion of a 2D-DCT architecture using coefficient distributed arithmetic [implementaion read implementation]

Leakage power driven behavioral synthesis of pipelined datapaths

High speed max-log-MAP turbo SISO decoder implementation using branch metric normalization

A nonlinear programming based power optimization methodology for gate sizing and voltage selection

Adaptive power management in software radios using resolution adaptive analog to digital converters

Using the nonlinear property of FSR and dictionary coding for reduction of test volume

Low cost test vector compression/decompression scheme for circuits with a reconfigurable serial multiplier

Fault diagnosis and fault model aliasing

PASSAT: efficient SAT-based test pattern generation for industrial circuits

Self-refereed on-chip jitter measurement circuit using Vernier oscillators

IR drop and ground bounce awareness timing model

Design and implementation of FPGA router for efficient utilization of heterogeneous routing resources

Post-placement pin optimization

A low power embedded dataflow coprocessor

Reduction of direct tunneling power dissipation during behavioral synthesis of nanometer CMOS circuits

Sensitivity analysis of a cluster-based interconnect model for FPGAs

Analysis of incremental communication for multilayer neural networks on a field programmable gate array

Reduction of power and test time by removing cluster of don't-care from test data set

Evaluating the data integrity of memory systems by configurable Markov models

Synthesis of self-resetting stage logic pipelines

Energy efficient architectures for the log-MAP decoder through intelligent memory usage

RAMS: a VHDL-AMS code refactoring tool supporting high level analog synthesis

Pipelined memory controllers for DSP applications handling unpredictable data accesses

The use of pre-evaluation phase in dynamic CMOS logic

Configurable multiprocessors for high-performance MPEG-4 video coding

Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs

Wire length distribution model considering core utilization for system on chip

12-23 GHz ultra wide tuning range voltage-controlled ring oscillator with hybrid control schemes

A flexible and efficient hardware architecture for real-time face recognition based on eigenface

A high performance hybrid wave-pipelined multiplier

Towards integration of quadratic placement and pin assignment

Balancing system level pipelines with stage voltage scaling

Reducing the communication bottleneck via on-chip cosimulation of gate-level HDL and C-models on a hardware accelerator

Design of a QCA memory with parallel read/serial write

RG-SRAM: a low gate leakage memory design

Increasing data TLB resilience to transient errors

RITC: repeater insertion with timing target compensation

Design of a real time system for nonlinear enhancement of video streams by an integrated neighborhood dependent approach

An efficient VLSI architecture for 2-D convolution with quadrant symmetric kernels

A new organization for a perceptron-based branch predictor and its FPGA implementation

A hierarchical method for wiring congestion prediction

CMOS realization of online testable reversible logic gates

A scalable parallel SoC architecture for network processors

A comparative study on dicing of multiple project wafers

IEEE Computer Society Annual Symposium on VLSI

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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