NDLI: 3D transistors

Please wait, while we are loading the content...

2015 International Symposium on VLSI Technology, Systems and Applications

Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

M2M: Challenges and opportunities

Innovations in healthcare and semiconductor progress

To 4G mobile communication and beyond

Multimode multiband power amplifier optimization for mobile applications

FDSOI: A differentiator for application processors in consumer and mobile markets

$UltraCMOS^{®}$ technology for high-performance switch paths and tunable components

RF and signal processing technologies for 4G mobile networks

Ultra-low-power switching and complementary resistive switching RRAM by single-stack metal-oxide dielectric

Sub-10nm 1T-1R cell design using HfO based ReRAM cell

Microscopic model for the kinetics of the reset process in HfO RRAM

Improved resistive switching memory performance using novel W/TaON/TiN structure

Good memory performance and coexistence of bipolar and unipolar resistive switching for CMOS compatible Ti/HfO/W memory

Rough surface improved formation-free low power resistive switching memory using IrO/W structure

Scalability issue in Ti/HfO bipolar resistive memory with 1T-1R configuration by resistance pinning effect during $1^{st}$ RESET and its solution

Improvement of switching uniformity and scalability in 1T-1R HfO-based bipolar resistive memory with Zr inserting layer

On the potential of CRS, 1D1R, and 1S1R crossbar RRAM for storage-class memory

Study of ambient effect in active SiO-based resistive switching memory

28nm high-k metal gate RRAM with fully compatible CMOS logic processes

Multi-level resistive switching characteristics correlated with microscopic filament geometry in TMO-RRAM

Advanced SPICE modeling for program inhibit operation in NAND flash memories

Multilevel ultra-fast and disturb-free flash memory with double embedded Au and Gd nanocrystals

Self-align nitride based logic NVM in 28nm high-k metal gate CMOS technology

Demonstration of chip level writability, endurance and data retention of an entire 8Mb STT-MRAM array

The understanding of the bulk trigate MOSFET's reliability through the manipulation of RTN traps

Investigations on the gate oxide dependence of AC RTN characteristics in nanoscaled MOSFETs: SiON vs. HfO

Random telegraph signal noise arising from grain boundary traps in nano-scale poly-Si nanowire thin-film transistors

Impacts of cycle-to-cycle variation effects on the prediction of NBTI degradation and the resulted dynamic variations in high-к MOSFETs

The design optimization and variation study of segmented-channel MOSFET using HfO or SiO trench isolation

The series resistance component of hot carrier degradation in ultra-short channel devices

Effect of ALD oxidant and channel doping on positive bias stress characteristics of surface channel InAs nMOSFETs

EUV degradation of high performance Ge MOSFETs

Transformation of VLSI technologies, systems and applications the rise of foundry and its ecosystem

Device design considerations for next generation CMOS technology: Planar FDSOI and FinFET (Invited)

Suppressed variability of current-onset voltage of FinFETs by improvement of work function uniformity of metal gates

(110)-oriented germanium-tin (Ge) P-channel MOSFETs

Schottky barrier free NiSi/Si junction technology by Yb-implantation for 1xnm CMOS applications

Novel technique comprising silane treatment and laser anneal for abrupt ultra-shallow junction formation for InGaAs n-MOSFETs

Sub-10nm junction in InGaAs with sulfur mono-layer doping

A comparative study of gate first and last Si MOSFETs fabrication processes using ALD beryllium oxide as an interface passivation layer

Device scalability and electrical properties of ALD HfZrO with optimum plasma nitridation technique: A study of depth profiles by maximum entropy finite element model and gate stack sub-band gap extraction

Enabling thermal IL and ALD HfOx integration for sub-20nm gate stack

Ultralow EOT and high mobility Ge pMOSFETs with in-situ HO plasma grown GeO and HfON gate dielectric

Germanium-Tin (GeSn) N-channel MOSFETs with low temperature silicon surface passivation

New integration schemes for 2,5D interposer

Comprehensive study for RF interference limited 3D TSV optimization

Study of TSV filling performance with wide-range pattern densities by using a novel plating chamber with surface paddle agitation

Co-sputtered Cu/Ti bonded interconnects for 3D integration applications

Short channel poly-Ge junction-less p-type FinFETs for BEOL transistors

What happens when circuits grow old: Aging issues in CMOS design

Improving and optimizing reliability in future technologies with high-κ dielectrics

Microscopic degradation models for advanced technology

CMOS reliability: From discrete device degradation to circuit aging

Opportunities and challenges of 3D NAND scaling

Bit Cost Scalable (BiCS) technology for future ultra high density memories

SoC level considerations of 3D technology architecture

Low temperature FDSOI devices, a key enabling technology for 3D sequential integration

High-performance fully transparent Ga-doped ZnO TFTs fabricated by RF Magnetron Sputtering

6-T SRAM cell design with gate-all-around silicon nanowire MOSFETs

Design and optimization of 6T SRAM using vertically stacked nanowire MOSFETs

Analysis of Germanium FinFET logic circuits and SRAMs with asymmetric gate to source/drain underlap devices

Effect of fin height of tapered FinFETs on the sub-22-nm System on Chip (SoC) application using TCAD simulation

Laser anneal assisted contact resistivity reduction with post-silicide implantation for 14nm node and beyond

Modeled specific contact resistivity with high doping effects: Requirements for 1 $nΩ-cm^{2}$ contacts

Source/drain series resistance induced feedback effect on drain current mismatch and its implication

A perspective on future nanoelectronic devices

Dark current and white blemish in image sensors

CMOS image sensor design methodology

SNR metric and crosstalk in color image sensor of small size pixel

Challenges and opportunities in small pixel development for novel CMOS image sensors

CMOS image sensor technology development for system-level optimization

Smart Cut™ technology provides excellent layer uniformity for fully depleted CMOS

Junction engineering for FDSOI technology speed/power enhancement

Analysis of threshold voltage shifts in double gate tunnel FinFETs: Effects of improved electrostatics by gate dielectrics and back gate effects

Random interface trap induced fluctuation in 22nm high-k/metal gate junctionless and inversion-mode FinFETs

Low power negative capacitance FETs for future quantum-well body technology

Is the bulk vs. SOI battle over?

Proceedings of Technical Program of 2012 VLSI Technology, System and Application

Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications

Proceedings of 2010 International Symposium on VLSI Technology, System and Application

2009 International Symposium on VLSI Technology, Systems, and Applications

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

2006 International Symposium on VLSI Technology, Systems, and Applications

IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech).

2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672)

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)

Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications

1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers

1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers

1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers

International Symposium on VLSI Technology, Systems and Applications,

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in