NDLI: Architecture for VLSI design of CA based byte error correcting code decoders

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Architecture for VLSI design of CA based byte error correcting code decoders

Content Provider	IEEE Xplore Digital Library
Author	Chowdhury, D.R. Chaudhuri, P.P.
Copyright Year	1994
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India (Chowdhury, D.R.; Chaudhuri, P.P.)
Abstract	This paper reports a novel architecture for byte error correcting code decoders using Cellular Automata (CA). The chip architecture of the basic building blocks for double byte error locating/correcting code (DbEL/DbEC) is presented. Extension of the architecture to detect arbitrary number of byte errors has also been included. The proposed decoder provides a simple, modular, cascadable and cost effective design that is ideally suited for VLSI implementation.
Starting Page	283
Ending Page	286
File Size	315463
Page Count	4
File Format	PDF
ISBN	0818649909
ISSN	10639667
DOI	10.1109/ICVD.1994.282703
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-01-05
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Error correction codes Decoding Computer architecture Computer science Reed-Solomon codes Error correction Hardware Buildings Costs
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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